Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
1998-10-26
2002-01-22
Ellis, Kevin L. (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
Reexamination Certificate
active
06341334
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a bridge method and a bus bridge for bridging a plurality of buses, and a multiprocessor system utilizing the bridge method and bus bridge.
2. Description of the Related Art
A close-coupled system, which is a system of a plurality of processors connected to a single bus, is a typical example of a multiprocessor system capable of executing in parallel a plurality of processors. However, such a system has a shortcoming in that the number of processors in the system cannot be increased beyond a certain physical upper limit because of constraints on the number that can be connected to a single bus due to the load capacity of bus signal lines. In comparison, a multiprocessor system described in Japanese Laid-Open Patent Publication No. Hei 9-128346 has a configuration in which a plurality of buses are mutually connected with bus bridges, the advantage being that although the number of processors that can be connected to each bus can be limited to within the above-mentioned physical upper limit, the overall system can operate more processors in parallel than the above-mentioned physical upper limit. Namely, the system relating to the above-mentioned publication can include more participating processors, than the close-coupled system.
However, when a device is to receive data from another device in the multiprocessor system described in the above-mentioned publication, the device that is to receive the data may be made to wait temporarily, thus resulting in a delay in processing so as to become an impediment in improving system performance.
An example can be considered where a processor connected to a first bus is to read data from an arbitrary address in a memory connected to a second bus. In response to receiving a data read request from the reading processor via the first bus, a bus bridge connecting the first bus to the second bus transmits a data read request to the second bus. This bus bridge receives data from the memory via the second bus and transmits the data to the first bus. Thus, after the data read request is transmitted to the first bus and until the data is received, the reading processor cannot execute any processing regarding the data. Cache memories usually found at each processor and bus bridge are useful to shorten this idle time, e.g. the use of the bridge cache (called the cache memory for the bus bridge) together with an appropriate bus snoop technique can eliminate the process for requesting data on the memory from the bus bridge via the second bus. However, when executing a program in which the cache hit rate for the bridge cache is low, namely, a program that often requests data not found in the bridge cache, the drop in system performance due to the above-mentioned delay becomes particularly noticeable.
SUMMARY OF THE INVENTION
One object of the present invention is to suppress delays in processing as well as the resulting drop in system performance caused by the idle waiting of a device, such as a processor, that has requested data.
A first aspect of the present invention is a bridge method having a predictive cache process and a response process. In the predictive cache process, on the basis of the contents of a request signal predicted to be issued in the future from a device connected to a first bus, a request signal (an anticipatory request signal) is transmitted onto a second bus to which a device or devices are connected, to request data. Namely, according to a prediction where the device connected to the first bus will issue a signal for requesting data held by any one of the devices connected to the second bus, in the predictive cache process, an anticipatory request signal is issued and transmitted onto the second bus to which the various types of devices including the device or devices holding the requested data are connected, and thus the data is cached, from any one of devices holding the data and connected to the second bus, into a bridge cache.
In the response process, when the data requested by a request signal actually issued from the device connected to the first bus is found in the bridge cache, the data is sent from the bridge cache to the device that issued the request signal.
One case where the data concerning the request signal issued from a device connected to the first bus has already been cached into the bridge cache is a case where the data is already cached into the bridge cache by execution of the predictive cache process. Therefore, according to this aspect, the frequency at which the data can be sent immediately to the device originating the request signal increases and at the same time the frequency at which the device originating the request signal is forced to wait decreases, so that processing delays decrease and system performance improves. Also, since wait instructions are furnished at a lower frequency to the device originating the request signal, the load on the first bus decreases.
A second aspect of the present invention is a bus bridge comprising a bridge cache, a request prediction unit, a cache hit judgment unit, a response generator, and a request issuer. The bridge cache is a cache memory for caching the data held in the devices connected to the first or second bus. The request prediction unit, the cache hit judgment unit, and the request issuer provide functions relating to the predictive cache process in the first aspect. The cache hit judgment unit and the request issuer provide functions relating to the response process in the first aspect.
First, the request prediction unit predicts the contents of the request signal to be issued in the future from a device connected to the first bus and issues a prediction signal indicating the contents of the predicted request signal. When the prediction signal is issued from the request prediction unit, the cache hit judgment unit judges whether or not the data requested by the prediction signal is found in the bridge cache. With regard to the prediction signal issued from the request prediction unit, when it was judged that the data requested by the prediction signal is not found in the bridge cache, the request issuer issues a request signal for requesting the data to the device or devices connected to the second bus. Therefore, if there is a device (or devices) responding to the request signal with the requested data, data predicted to be requested in the future from the device connected to the first bus is cached into the bridge cache in advance of any actual request.
When a request signal is actually issued from the device connected to the first bus, the cache judgment unit judges whether or not the data requested by the request signal is found in the bridge cache. If found, the bus bridge can respond with the data to the device originating the request. Conversely, for the request signal actually issued from the device connected to the first bus, when it is judged the data requested by the request signal is not found in the bridge cache, the response generator on one hand issues a response signal to the device that issued the request signal to instruct the device to wait for a subsequent transmission of that data, while the request issuer on the other hand issues a request signal for requesting that data to the device or devices connected to the second bus. Namely, the device originating the request is made to temporarily wait, during which time the requested data is cached into the bridge cache.
Therefore, with regard to the request signal actually issued from the device connected to the first bus and judged as the requested data is not found in the bridge cache, the frequency at which the device originating the request is forced to temporarily wait is lower than the related art as a result in this aspect. This is realized by the provision of the request prediction unit and the inclusion of the prediction signal, in addition to the request signal that was actually issued for processing, by the cache hit judgment unit and the request issuer. As a result, processing delays caused by a d
Ellis Kevin L.
Leydig , Voit & Mayer, Ltd.
Mitsubishi Denki & Kabushiki Kaisha
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