Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
2007-12-25
2007-12-25
Ha, Nathan W (Department: 2814)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Reexamination Certificate
active
10904423
ABSTRACT:
A chip package having at least a substrate, a chip and a conductive trace is provided. The substrate has a first surface, a second surface, a cavity and at least one substrate contact all positioned on the first surface of the substrate. The chip has an active surface with at least one chip contact thereon. The chip is accommodated inside the cavity with at least one sidewall having contact with one of the sidewalls of the cavity. The active surface of the chip and the first surface of the substrate are coplanar. The conductive trace runs from the active surface of the chip to the first surface of the substrate so that the chip contact and the substrate contact are electrically connected.
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Advanced Semiconductor Engineering Inc.
Ha Nathan W
Jianq Chyun IP Office
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