Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package
Reexamination Certificate
2003-06-20
2004-12-21
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
C257S701000, C257S712000, C257S723000, C257S787000, C438S118000, C438S124000, C438S126000, C174S260000
Reexamination Certificate
active
06833610
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
This application claims the priority benefit of Taiwan application serial no. 91123066, filed Oct. 7, 2002.
BACKGROUND OF INVENTION
1. Field of Invention
The present invention relates to a type of chip package and fabricating method. More particularly, the present invention relates to a bridge connection type of chip package and fabricating method thereof for improving electrical performance.
2. Description of Related Art
Accompanying the rapid progress in electronic technologies, more personalized and functionally powerful electronic products are developed. To facilitate use and enhance portability, most electronic products are designed to have a lighter weight and a smaller size. Whether a given electronic product can be miniaturized depends largely on the size of the chip package embedded inside. In general, electrical connections between a silicon chip and a carrier in a chip package can be roughly divided into three major types including wire bonding, tape automated bonding (TAB) or flip chip. The connection between the contact on a chip and the contact on a carrier is made in a few sequential steps using a bonding machine. First, the bonding head of a bonding machine is driven over the contact of a chip. An electric discharge is produced near the tip of the bonding head to melt the end of the wire into a spherical ball. The spherical ball is lowered onto a chip contact to form a bond. Thereafter, the bonding head is raised pulling out additional wire from a wire spool. Finally, ultrasound is applied to melt the other end of the wire while the wire is lowered onto carrier contact.
FIG. 1
is a cross-sectional view of a chip package having a conventional wire-bonding structure. A package structure
100
having a substrate
120
, a chip
160
, a plurality of conductive wires
170
, an encapsulation
180
and a plurality of solder balls
190
is shown in FIG.
1
. The substrate
120
has a first surface
122
and a second surface
124
. The substrate
120
has a number of substrate contacts
126
,
128
and a die pad
132
. The contact
126
and the die pad
132
are formed on the first surface
122
of the substrate
120
. The substrate contact
126
surrounds the die pad
132
. The substrate contact
128
is formed on the second surface
124
of the substrate
120
. The chip
160
has an active surface
162
and a backside
164
. The chip
160
has a number of chip contacts
166
all on the active surface
162
. The backside
164
of the chip
160
is attached to the die pad
132
of the substrate
120
through an adhesive material
140
. The chip
160
and the substrate
120
are electrically connected using conductive wires positioned after a wire bonding process. One end of the conductive wire
170
is bonded to the chip contact
166
while the other end of the conductive wire
170
is bonded to the substrate contact
126
. The encapsulation
180
encloses the chip
160
, the first surface
122
of the substrate
120
and the conductive wires
170
. The solder balls
190
are attached to the substrate contacts
128
. Through the solder balls
190
, the package
100
is able to connect electrically with an external circuit (not shown).
In the aforementioned package
100
, the chip
160
and the substrate
120
are electrically connected through conductive wires
170
. Since a conductive wire has a relatively small cross-sectional area and long length, resistant mismatch often results in signal decay. At high-frequency signaling operation, in particular, parasitic induction-capacitance in the wire may result in signal reflection. Furthermore, the small sectional area in the conductive pathway at the junction between the conductive wire
170
and the substrate contact
126
or the chip contact
166
often affects the standard power or ground voltage as well as current that ought to be supplied to the package.
SUMMARY OF INVENTION
Accordingly, one object of the present invention is to provide a chip package structure and fabricating method thereof capable of shortening the electrical connections between a chip and a substrate so that electrical performance of the package is improved.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a chip package structure. The package includes a substrate, a silicon chip, at least one conductive trace and a plurality of solder balls. The substrate has a first surface and a second surface. The substrate also has a cavity and at least one substrate contact on the first surface of the substrate. The silicon chip has an active surface with at least one chip contact thereon. The chip is positioned inside the cavity of the substrate. At least one sidewall of the chip is next to one of the sidewalls of the cavity. The active surface of the chip and the first surface of the substrate are on the same level plane. The conductive trace is an extension on the active surface of the chip and the first surface of the substrate for connecting a chip contact and a substrate contact together electrically.
According to one preferred embodiment of this invention, the chip package further includes an encapsulation that encloses the active surface of the chip, the first surface of the substrate and the conductive trace. The chip contact is located near the edge of the chip and the substrate contact is located near the edge of the cavity of the substrate. The chip contact and the substrate contact are close to each other. In addition, the cavity can be designed to have a cross-sectional dimension similar to the chip. Moreover, the material of the conductive trace is, for example, lead-tin alloy, tin, lead-free conductive material or conductive plastics.
This invention also provides a method of forming a bridge connection between a silicon chip and a carrier. The method includes the following steps. First, a carrier and a chip are provided. The carrier has a cavity on one side of the carrier. The chip has an active surface. The chip is placed inside the cavity of the carrier such that the active surface of the chip and the surface of the carrier are flush with each other on the same plane. In addition, one of the sidewalls of the chip is pressed against a sidewall of the cavity. At least one conductive trace that extends from the active surface of the chip to the surface of the carrier is formed so that the chip and the carrier are electrically connected carrier can be a substrate, for example.
According to one preferred embodiment of this invention, the conductive trace may be fabricated in one of three ways.
The first method includes depositing solder material onto the active surface of the chip and the surface of the carrier by screen-printing. Thereafter, a solder reflow process is conducted to consolidate the solder material into the conductive trace.
The second method includes forming a patterned mask over the active surface of the chip and the surface of the carrier. The patterned mask has at least one opening that exposes the active surface of the chip and the surface of the carrier. A printing method is used to deposit solder material into the opening of the patterned mask. Thereafter, a solder reflow process is conducted to consolidate the solder material into the conductive trace. Finally, the patterned mask is removed. The patterned mask can either be a photosensitive material or a non-photosensitive material.
The third method includes smearing conductive silver paste onto the chip and the carrier. Thereafter, a baking process is conducted to turn the silver paste into a conductive trace so that the chip and the carrier are electrically connected.
This invention also provides an alternative method of forming a bridge connection between a silicon chip and a carrier. The method includes the following steps. First, a carrier and a chip are provided. The carrier has a cavity on one side of the carrier and at least a contact on the surface of the carrier close to the opening edge of the cavity. The chip also ha
Advanced Semiconductor Engineering Inc.
Jianq Chyun IP Office
Nelms David
Tran Mai-Huong
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