Patent
1994-11-30
1996-09-17
Harvey, Jack B.
395306, G06F 1300
Patent
active
055577580
ABSTRACT:
A bridge is provided between an industry standard architecture (ISA) bus and a peripheral controller interconnect (PCI) bus and performs memory cycles on both buses simultaneously when a master on the ISA bus initiates a memory transfer. Data is steered between the ISA and PCI buses when a slave on the PCI bus claims the memory address within a predetermined time period after the memory cycle is initiated on the PCI bus. The ISA bus is isolated from the PCI bus when no slave on the PCI bus claims the memory address. This allows the memory cycle to be completed on the ISA bus, and the memory cycle on the PCI bus is terminated.
REFERENCES:
patent: 5191653 (1993-03-01), Banks et al.
patent: 5191657 (1993-03-01), Ludwig et al.
patent: 5446869 (1995-08-01), Padgett et al.
"82420/82430 PCIset ISA and EISA Bridges", Intel, Dec. 1993, pp. 15-19.
"Peripheral Component Interconnect", Revision I.O. Specification, Dec. 1992, Section 3.6.1.
Bland Patrick M.
Hofmann Richard G.
Katz Sagi
Moeller Dennis
Venarchick Lance M.
Harvey Jack B.
International Business Machines - Corporation
Magistrale Anthony N.
McConnell Daniel E.
Wiley David A.
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