Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2005-10-11
2005-10-11
Beausoliel, Robert (Department: 2113)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C717S129000
Reexamination Certificate
active
06954878
ABSTRACT:
A microcomputer11with a debug circuit11bimplemented therein for realizing an on-chip debugging function is mounted on a target board10in which a variety of buses15are led out and connected to a break board30. The break board30is provided with a break condition storage section31and a break signal generation section32. Break conditions are written in the break condition storage section31from the side of a debugger20through the debug circuit11b, the CPU11aand the various buses15. Then, a user program stored in a ROM12is executed. The break signal generation section32monitors signals on the various buses15, and outputs a break generation signal30awhen the signals on the various buses15coincide with the break condition. The execution of the user program is interrupted (stopped) based on the break generation signal30a.
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“Nikkei Electronics”, Mar. 22, 1999, pp. 215-225 (with translation).
Beausoliel Robert
McCarthy Christopher
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