Branch target address cache including address type tag bit

Details Branch target address cache including address type tag bit Branch target address cache including address type tag bit

2011-01-04

2011-01-04

Pan, Daniel (Department: 2183)

Electrical computers and digital processing systems: processing

Processing control

Branching

C712S240000

Reexamination Certificate

active

07865705

ABSTRACT:
In at least one embodiment, a processor includes an execution unit and instruction sequencing logic that fetches instructions from a memory system for execution by the execution unit. The instruction sequencing logic includes branch logic that outputs predicted branch target addresses for use as instruction fetch addresses. The branch logic includes a branch target address prediction circuitry concurrently holding a first entry providing storage for a first branch target address prediction associating a first instruction fetch address with a first branch target address to be used as an instruction fetch address and a second entry providing storage for a second branch target address prediction associating the first instruction fetch address with a different second branch target address. The first entry indicates a first instruction address type for the first instruction fetch address, and the second entry indicates a second instruction address type for the first instruction fetch address.

REFERENCES:
patent: 6279105 (2001-08-01), Konigsburg et al.
patent: 6279106 (2001-08-01), Roberts
patent: 6353882 (2002-03-01), Hunt
patent: 6484256 (2002-11-01), Levitan et al.
patent: 6516409 (2003-02-01), Sato
patent: 6611910 (2003-08-01), Sharangpani et al.
patent: 6823447 (2004-11-01), Hay et al.
patent: 2002/0178349 (2002-11-01), Shibayama et al.
patent: 2002/0199092 (2002-12-01), Henry et al.
patent: 2005/0027967 (2005-02-01), Sperber et al.
patent: 2005/0091475 (2005-04-01), Sodami
patent: 2005/0262332 (2005-11-01), Rappoport et al.
patent: 2006/0174096 (2006-08-01), Konigsburg et al.
patent: 2006/0221960 (2006-10-01), Borgione
patent: 2006/0236080 (2006-10-01), Doing et al.
patent: 2007/0033318 (2007-02-01), Gilday et al.
patent: 2008/0046702 (2008-02-01), Morrow
patent: 462587 (1991-12-01), None
Levitan et al.; “Data Processing System, Processor and Method of Data Processing Having Improved Branch Target Address Cache”; U.S. Appl. No. 11/837,893, filed Aug. 13, 2007.
Bradford et al.; “Data Processing System, Processor and Method of Data Processing Having Improved Branch Target Address Cache”; U.S. Appl. No. 11/561,002, filed Nov. 17, 2006.
Eberly Jr. et al.; “The Correlation Branch Target Address Cache”; IBM TDB, vol. 36, No. 5, pp. 83-86, May 1996.
Eickenmeyer; “Improving Instruction Cache Branch Prediction with Target Addresses”; IBM TDB, vol. 36, No. 7, pp. 497-498, Jul. 1993.

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