Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1996-02-27
1998-11-10
Chan, Eddie P.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711128, 711158, G06F 1208
Patent
active
058359516
ABSTRACT:
An up/dn read prioritization protocol is used to select between multiple hits in a set associative cache. Each set has associated with it an up/dn priority bit that controls read prioritization for multiple hits in the set--the up/dn bit designates either (i) up prioritization in which the up direction is used to select the entry with the lowest way number, or (ii) dn prioritization in which the down direction is used to select the entry with the highest way number. For each new entry allocated into the cache, the state of the up/dn priority bit is updated such that, for the next cache access resulting in multiple hits, the read prioritization protocol selects the new entry for output by the cache.
REFERENCES:
patent: 4942520 (1990-07-01), Langendorf
patent: 5347642 (1994-09-01), Barratt
patent: 5353424 (1994-10-01), Partovi et al.
Chan Eddie P.
Ellis Kevin L.
Maxin John L.
National Semiconductor
Viger Andrew S.
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