Branch prediction within a multithreaded processor

Details Branch prediction within a multithreaded processor Branch prediction within a multithreaded processor

2011-01-25

2011-01-25

Chan, Eddie P (Department: 2183)

Electrical computers and digital processing systems: processing

Processing control

Branching

Reexamination Certificate

active

07877587

ABSTRACT:
A branch prediction mechanism16, 18within a multithreaded processor having hardware scheduling logic6, 8, 10, 12uses a shared global history table18which is indexed by respective branch history registers20, 22for each program thread. Different mappings are used between preceding branch behavior and the prediction value stored within respective branch history registers20, 22. These different mappings may be provided by inverters placed into the shift in paths for the branch history registers20, 22or by adders40, 42or in some other way. The different mappings help to equalise the probability of use of the particular storage locations within the global history table18such that the plurality of program threads are not competing excessively for the same storage locations corresponding to the more commonly occurring patterns of preceding branch behavior.

REFERENCES:
patent: 2004/0215720 (2004-10-01), Alexander et al.
Ramsay et al.; Exploring Efficient SMT Branch Predictor Design; Jun. 2003; ISCA '03.
McFarling; Combining Branch Predictors; 1993.

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