Electrical computers and digital processing systems: processing – Processing control – Branching
Reexamination Certificate
2008-04-24
2011-12-13
Faherty, Corey S (Department: 2183)
Electrical computers and digital processing systems: processing
Processing control
Branching
C712S240000
Reexamination Certificate
active
08078850
ABSTRACT:
Methods, apparatus, and products for branch prediction in a computer processor are disclosed that include: recording for a sequence of occurrences of a branch, in an algorithm in which the branch occurs more than once, each result of the branch, including maintaining a pointer to a location of a most recently recorded result; resetting the pointer to a location of the first recorded result upon completion of the algorithm; and predicting subsequent results of the branch, in subsequent occurrences of the branch, in dependence upon the recorded results.
REFERENCES:
patent: 4813037 (1989-03-01), Debuysscher et al.
patent: 4951195 (1990-08-01), Fogg et al.
patent: 5167023 (1992-11-01), De Nicolas et al.
patent: 5301302 (1994-04-01), Blackard et al.
patent: 5590308 (1996-12-01), Shih
patent: 5761516 (1998-06-01), Rostoker et al.
patent: 5870479 (1999-02-01), Feiken et al.
patent: 5884060 (1999-03-01), Vegesna et al.
patent: 5974498 (1999-10-01), Hopkins
patent: 6047122 (2000-04-01), Spiller
patent: 6049866 (2000-04-01), Earl
patent: 6085315 (2000-07-01), Fleck et al.
patent: 6101599 (2000-08-01), Wright et al.
patent: 6145072 (2000-11-01), Shams et al.
patent: 6151668 (2000-11-01), Pechanek et al.
patent: 6164841 (2000-12-01), Mattson et al.
patent: 6292888 (2001-09-01), Nemirovsky et al.
patent: 6446171 (2002-09-01), Henriksen
patent: 6519605 (2003-02-01), Gilgen et al.
patent: 6567895 (2003-05-01), Scales
patent: 6625662 (2003-09-01), Satoh et al.
patent: 6668308 (2003-12-01), Barroso et al.
patent: 6675284 (2004-01-01), Warren
patent: 6725317 (2004-04-01), Bouchier et al.
patent: 6823429 (2004-11-01), Olnowich
patent: 6832184 (2004-12-01), Bleier et al.
patent: 6891828 (2005-05-01), Ngai
patent: 6915402 (2005-07-01), Wilson et al.
patent: 6950438 (2005-09-01), Owen et al.
patent: 6973032 (2005-12-01), Casley et al.
patent: 6988149 (2006-01-01), Odenwald
patent: 7010580 (2006-03-01), Fu et al.
patent: 7072996 (2006-07-01), Adusumilli et al.
patent: 7162560 (2007-01-01), Taylor et al.
patent: 7376789 (2008-05-01), Halleck et al.
patent: 7394288 (2008-07-01), Agarwal
patent: 7398374 (2008-07-01), DeLano
patent: 7464197 (2008-12-01), Ganapathy et al.
patent: 7493474 (2009-02-01), Pechanek et al.
patent: 7500060 (2009-03-01), Anderson et al.
patent: 7502378 (2009-03-01), Lajolo et al.
patent: 7521961 (2009-04-01), Anderson
patent: 7533154 (2009-05-01), Chen et al.
patent: 7546444 (2009-06-01), Wolrich et al.
patent: 7568064 (2009-07-01), Rablewski et al.
patent: 7590774 (2009-09-01), Johns et al.
patent: 7664108 (2010-02-01), Bahattab
patent: 7689738 (2010-03-01), Williams et al.
patent: 2002/0099833 (2002-07-01), Steely et al.
patent: 2002/0178337 (2002-11-01), Wilson et al.
patent: 2003/0065890 (2003-04-01), Lyon
patent: 2004/0083341 (2004-04-01), Robinson et al.
patent: 2004/0088487 (2004-05-01), Barroso et al.
patent: 2004/0151197 (2004-08-01), Hui
patent: 2004/0250046 (2004-12-01), Gonzalez et al.
patent: 2004/0260906 (2004-12-01), Landin et al.
patent: 2005/0086435 (2005-04-01), Todoroki
patent: 2005/0166205 (2005-07-01), Oskin et al.
patent: 2005/0198442 (2005-09-01), Mandler
patent: 2005/0203988 (2005-09-01), Nolle et al.
patent: 2005/0238035 (2005-10-01), Riley
patent: 2006/0209846 (2006-09-01), Clermidy et al.
patent: 2006/0242393 (2006-10-01), Park et al.
patent: 2007/0055826 (2007-03-01), Morton et al.
patent: 2007/0074191 (2007-03-01), Geisinger
patent: 2007/0076739 (2007-04-01), Manjeshwar et al.
patent: 2007/0271557 (2007-11-01), Geisinger
patent: 2007/0283324 (2007-12-01), Geisinger
patent: 2008/0028401 (2008-01-01), Geisinger
patent: 2008/0134191 (2008-06-01), Warrier et al.
patent: 2008/0186998 (2008-08-01), Rijpkema
patent: 2008/0216073 (2008-09-01), Yates et al.
patent: 2009/0083263 (2009-03-01), Felch et al.
patent: 2009/0282222 (2009-11-01), Hoover et al.
patent: 1599471 (2005-03-01), None
Office Action Dated Jan. 29, 2010 in U.S. Appl. No. 11/945,396.
Final Office Action Dated Jan. 15, 2010 in U.S. Appl. No. 12/031,733.
David Taylor, et al. “System on Chip Packet Processor for an Experimental Network Service Platform”. 2003.
Office Action Dated Mar. 30, 2010 in U.S. Appl. No. 11/926,212.
Final Office Action Dated May 19, 2010 in U.S. Appl. No. 11/945,396.
INTEL, E8870 Chipset, Intel, Jun. 2002, pp. 1-10.
Office Action Dated Apr. 2, 2010 in U.S. Appl. No. 11/955,553.
Kumar, et al. “A Network on Chip Architecture and Design Methodology”. Published 2002, pp. 1-8, ISBN 0-7695-1486-03/02 by IEEE.
Bolotin, et al. “The Power of Priority: NoC based Distributed Cache Coherency”. Published May 21, 2007, pp. 117-126, ISBN 0-7695-2773-06/07 by IEEE.
Office Action Dated Mar. 24, 2010 in U.S. Appl. No. 12/031,733.
Virtanen, et al. “NoC Interface for a Protocol Processor”. University of Turku.
Walter, et al., “BENoC: A Bus-Enhanced Network on-Chip”. Dec. 2007, Technion, Israel Institute of Technology, Haifa, Israel.
Office Action Dated Jun. 8, 2010 in U.S. Appl. No. 12/118,298.
Office Action Dated May 26, 2010 in U.S. Appl. No. 12/117,875.
U.S. Appl. No. 12/117,897, filed May 9, 2008, Hoover, et al.
U.S. Appl. No. 12/031,733, filed Feb. 15, 2008, Hoover, et al.
U.S. Appl. No. 12/108,846, filed Apr. 24, 2008, Kuesel, et al.
U.S. Appl. No. 12/108,770, filed Apr. 24, 2008, Mejdrich, et al.
U.S. Appl. No. 12/029,647, filed Feb. 12, 2008, Hoover, et al.
U.S. Appl. No. 12/118,017, filed May 9, 2008, Comparan, et al.
U.S. Appl. No. 12/118,059, filed May 9, 2008, Mejdrich, et al.
U.S. Appl. No. 12/117,875, May 9, 2008, Hoover, et al.
U.S. Appl. No. 12/121,222, May 15, 2008, Kriegel, et al.
U.S. Appl. No. 11/936,873, filed Nov. 8, 2007, Hoover, et al.
U.S. Appl. No. 12/135,364, filed Jun. 9, 2008, Hoover, et al.
U.S. Appl. No. 11/937,579, filed Nov. 9, 2007, Mejdrich, et al.
U.S. Appl. No. 12/102,033, filed Apr. 14, 2008, Heil, et al.
U.S. Appl. No. 12/118,272, filed May 9, 2008, Kuesel, et al.
U.S. Appl. No. 12/118,039, filed May 9, 2008, Hoover, et al.
U.S. Appl. No. 11/945,396, filed Nov. 27, 2007, Hoover, et al.
U.S. Appl. No. 12/015,975, filed Jan. 17, 2008, Comparan, et al.
U.S. Appl. No. 12/117,906, filed May 9, 2008, Hoover, et al.
U.S. Appl. No. 12/233,180, filed Sep. 18, 2008, Hoover, et al.
U.S. Appl. No. 12/113,286, filed May 1, 2008, Heil, et al.
U.S. Appl. No. 11/955,553, filed Dec. 13, 2007, Comparan, et al.
U.S. Appl. No. 12/031,738, filed Feb. 15, 2008, Hoover, et al.
U.S. Appl. No. 11/972,753, filed Jan. 11, 2008, Mejdrich, et al.
U.S. Appl. No. 12/060,559, filed Apr. 1, 2008, Comparan, et al.
U.S. Appl. No. 11/926,212, filed Oct. 29, 2007, Hoover, et al.
U.S. Appl. No. 12/118,298, filed May 9, 2008, Heil, et al.
U.S. Appl. No. 12/118,315, filed May 9, 2008, Mejdrich, et al.
U.S. Appl. No. 11/938,376, filed Nov. 12, 2007, Mejdrich, et al.
U.S. Appl. No. 12/121,168, filed May 15, 2008, Hoover, et al.
Office Action Dated Jul. 20, 2009 in U.S. Appl. No. 12/031,733.
Kuskin, et al.; The Stanford Flash Multiprocessor; Jun. 6, 1996; Stanford University.
Steve Furber, Future Trends in SOC Interconnect, Aug. 2000.
Bolotin, et al., The Power of Priority:NoC based Distributed Cache Coherency, May 21, 2007, IEEE, pp. 117-126.
Mereu, Gianni. “Conception, Analysis, Design and Realization of a Multi-socket Network-on-Chip Architecture and of the Binary Translation support for VLIW core targeted to Systems-on-Chip”, Mar. 2007, 145 pages, accessible at http://www.diee.unica.it/driei/tesi/19—mereu.pdf.
Huneycutt et al. “Software Caching using Dynamic Binary Rewriting for Embedded Devices”, 2001, Proceedings of the International Conference on Parallel Processing, 10 pages.
Cifuentes et al. “Walkabout—A Retargetable Dynamic Binary Translation Framework”, Sun Microsystems Laboratories, Jan. 2002, 13 pages.
Issenin et al.; (Date Reuse Driven Memory and network-on-Chip Co-Synthesis); NSF; pp. 1-7.
Kavaldijev et al. (“Providing QOS Guaranteed in a NOC by Virtual Channel Reservation”); 2006; pp. 1-12.
Monchiero (“Exploration of Distributed Shared
Kuesel Jamie R.
Kupferschmidt Mark G.
Mejdrich Eric O.
Schardt Paul E.
Biggers & Ohanian LLP
Faherty Corey S
International Business Machines - Corporation
LandOfFree
Branch prediction technique using instruction for resetting... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Branch prediction technique using instruction for resetting..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Branch prediction technique using instruction for resetting... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4270765