Branch prediction device with two levels of branch prediction ca

Details Branch prediction device with two levels of branch prediction ca Branch prediction device with two levels of branch prediction ca

1996-04-26

2000-05-23

Lim, Krisna

Electrical computers and digital processing systems: processing

Processing control

Branching

712235, 712247, 712236, 711119, G06F 930

Patent

active

060676167

ABSTRACT:
An improved branch prediction cache (BPC) scheme that utilizes a hybrid cache structure. The BPC provides two levels of branch information caching. The fully associative first level BPC is a shallow but wide structure (36 32-byte entries), which caches full prediction information for a limited number of branch instructions. The second direct mapped level BPC is a deep but narrow structure (256 2-byte entries), which caches only partial prediction information, but does so for a much larger number of branch instructions. As each branch instruction is fetched and decoded, its address is used to perform parallel look-ups in the two branch prediction caches.

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