Branch prediction architecture

Details Branch prediction architecture Branch prediction architecture

1998-10-16

2001-12-18

Ellis, Richard L. (Department: 2183)

Electrical computers and digital processing systems: processing

Processing control

Branching

C712S240000

Reexamination Certificate

active

06332189

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to computers. More particularly, the present invention relates to a branch prediction architecture.
2. Description of the Related Art
To maximize performance, modern computer designs attempt to execute as many instructions as possible concurrently. To find enough instructions to keep busy, the processors in modern computers use branch prediction to guess which instructions will be executed.
Branch prediction accuracy is a major performance factor in modern computer processor design. To improve branch prediction, various branch prediction strategies have been studied and implemented. See, for example, McFarling, “Serial Branch Prediction” (Nov. 1996); Su and Zhou, “A Comparative Analysis of Branch Prediction Schemes”, Computer Science Division, University of California at Berkeley (undated); Evers, Chang, and Patt, “Using Hybrid Branch Predictors to Improve Branch Prediction Accuracy in the Presence of Context Switches”, Department of Electrical Engineering and Computer Science, The University of Michigan (undated); Patel, Friendly, and Patt, “Critical Issues Regarding the Trace Cache Fetch Mechanism”, Advanced Computer Architecture Laboratory, Department of Electrical Engineering and Computer Science, The University of Michigan (undated); and Yeh, Marr, and Patt, “Increasing the Instruction Fetch Rate via Multiple Branch Prediction and a Branch Address Cache”, The 7th ACM International Conference on Supercomputing, Tokyo, Japan (July 1993). The sophisticated branch predictor implementations described in these papers use various different strategies, in various combinations, to achieve greater branch prediction accuracy.
The branch predictor is but one part, albeit an important part, of an overall branch prediction architecture. It is the overall branch prediction architecture's job to accurately and quickly guess which instructions will be executed, a job that becomes more and more complicated with each increase in computer speed, depth of pipeline, and number of instruction bundles. Although the known architectures are satisfactory for state-of-the-art microprocessors, they are not optimum for future processors that will be designed to process many more instructions concurrently, at much higher speeds.
The present invention is directed to overcoming, or at least reducing, these problems, and to provide a branch prediction architecture for future generation microprocessors.
SUMMARY OF THE INVENTION
According to one aspect of the present invention, provided is a branch prediction architecture having a branch predictor, a target address register, first and second selectors, and a memory. In operation, the first selector receives an output from the target address register, and provides an output to the memory. The memory receives an output from the branch predictor, as well as the output from the first selector, and in turn provides an output to the second selector. The second selector outputs branch predictions and instruction bundles.
According to another aspect of the present invention, a trace cache is included in the architecture. The trace cache receives the output from the branch predictor, and provides an output received by the second selector.


REFERENCES:
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S. McFarling, “Combining Branch Predictors,” Technical Note TN-36, DEC-WRL, Jun. 1993.*
E. Rotenberg et al. “Trace Cache: a low latency approach to high bandwidth instruction fetching,” Proceedings of the 29th International Symposium on Computer Architecture, Dec. 1996.*
Webster's II New Riverside Dictionary. Houghton Mifflin Company 1994; pp. 1-3.
McFarling, “Serial Branch Prediction,” (Nov. 1996).
Su and Zhou, “A Comparative Analysis of Branch Prediction Schemes,” (Undated).
Evers, Chang and Patt, “Using Hybrid Branch Predictors To Improve Branch Prediction Accuracy In The Presence Of Context Switches,” (Undated).
Patel, Friendly and Patt, “Critical Issues Regarding The Trace Cache Fetch Mechanism,” (Undated).
Yeh, Marr and Patt, “Increasing The Instruction Fetch Rate via Multiple Branch Prediction And A Branch Address Cache,” (Jul. 1993).

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