Electrical computers and digital processing systems: processing – Processing control – Branching
Reexamination Certificate
2006-09-06
2010-11-02
Li, Aimee J (Department: 2183)
Electrical computers and digital processing systems: processing
Processing control
Branching
C712S240000
Reexamination Certificate
active
07827393
ABSTRACT:
A branch prediction apparatus reads out a branch history table15by an index calculated by the output of a branch history register14containing a plurality of the latest branch result of a branch instruction. The branch prediction apparatus comprises frequency detection units18-20for detecting the appearance frequency of a branch instruction with a different address and data width modification units16and21for modifying the number of valid bits of the branch history register, based on the detected appearance frequency. Even a program in which a branch result strongly depends on the latest branch history or even a program having a plenty of branch instructions can maintain high prediction accuracy with a small capacity of the branch history table.
REFERENCES:
patent: 4943908 (1990-07-01), Emma et al.
patent: 5519841 (1996-05-01), Sager et al.
patent: 5553253 (1996-09-01), Pan et al.
patent: 5729726 (1998-03-01), Levine et al.
patent: 2002/0194460 (2002-12-01), Henry et al.
patent: 2002/0199091 (2002-12-01), Tago et al.
patent: 2007/0150712 (2007-06-01), Ali et al.
patent: 6-28184 (1994-02-01), None
patent: 10-240526 (1998-09-01), None
patent: 2002-163150 (2002-06-01), None
patent: 2003-5956 (2003-01-01), None
Supplemental European Search Report in EP 05 73 4503, mailed Apr. 2, 2008.
Juan T, et al., “Dynamic History-Length Fitting: A Third Level of Adaptivity for Branch Prediction”, Proceedings of the 25thAnn. Intl. Symposium on Computer Architecture, ISCA '98, Barcelona, Jun. 27- Jul. 1, 1998; Ann. International Symposium on Computer Architecture, Los Alamitos, CA; IEEE Computer Soc., US, Jun. 27, 1998, pp. 155-166, XP000849913; ISBN: 0-8186-8492-5.
Stark J., et al., “Variable Length Path Branch Prediction”, ACM Sigplan Notices, ACM, Assoc. for Computing Machinery, NY, NY, US, vol. 33, No. 11, Nov. 1998, pp. 170-179, XP000787306, ISSN: 0362-1340.
Tarlescu, M-D, et al., “Elastic History Buffer: A Low-Cost Method to Improve Branch Prediction Accuracy”, Proceedings of the Intl. Conference on Computer Design, VLSI in Computers and Processors, ICCD '97, Austin, TX, Oct. 12-15, 1997, Los Alamitos, CA: IEEE, US, Oct. 12, 1997, pp. 82-87, XP000799852, ISBN: 0-8186-8207-8.
Duesterwald, E., et al., “Characterizing and Predicting Program Behavior and Its Variability”, Parallel Architectures and Compilation Techniques, 2003. Pact 2003, Proceedings 12thInternational Conference on Sep. 27-Oct. 1, 2003, Piscataway, NJ, USA; IEEE Sep. 27, 2003, pp. 220-231, XP010662190, ISBN: 0-7695-2021-9.
“European official communication (Article 94(3) EPC)”, European Appln No. 05734503.5.
“European official communication”, mailed Jun. 25, 2009 from EU Patent Office, for corresponding EU Patent Application No. 05734503.5.
Fujitsu Limited
Fujitsu Patent Center
Li Aimee J
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