Branch metric computation and add-compare-select operation...

Details Branch metric computation and add-compare-select operation... Branch metric computation and add-compare-select operation...

2006-10-03

2006-10-03

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S786000, C714S793000, C714S792000

Reexamination Certificate

active

07117426

ABSTRACT:
An apparatus for branch metric computation and add-compare-select operation in a rate 1
Viterbi decoder with a constraint length of K. The apparatus of the invention includes a branch metric generator and an add-compare-select unit. The branch metric generator calculates a plurality of branch metrics each of which is a measure between a currently received data symbol and a corresponding branch label. The add-compare-select unit can generate respective decision bits for a pair of odd and even states at next instant with a novel pre-computational architecture. Further, a local winner between the odd and even states is predetermined in a manner providing reduction of the activity required by the computation. Thus the add-compare-select unit outputs a path metric of the local winner, whereby a saving of half the output number of path metrics is achieved.

REFERENCES:
patent: 5349608 (1994-09-01), Graham et al.
patent: 6813744 (2004-11-01), Traeber

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