Branch instruction prediction apparatus

Details Branch instruction prediction apparatus Branch instruction prediction apparatus

1997-06-24

1999-01-05

Treat, William M.

G06F 938

Patent

active

058570985

ABSTRACT:
The outcome of a given branch instruction is predicted using early and late branch history addressing modes. In an early addressing process, a first subset of bits from a branch history register is used to first address a branch history table to obtain a plurality of candidate predictions. In a late addressing process, a second subset of bits from the branch history register is used to again address the branch history table to select one of the plurality of candidate predictions, the second subset of bits including additional branch history information loaded into the branch history register subsequent to the early addressing mode. In this way, more recent branch history information is used to predict the outcome of the given branch instruction.

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patent: 5758143 (1998-05-01), Levitan
patent: 5774710 (1998-06-01), Chung

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