Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2000-05-10
2004-07-20
Myers, Paul R. (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S307000
Reexamination Certificate
active
06766404
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention generally relates to technologies for signal transmission between devices such as a multiprocessor and a memory in an information processor (e.g., between digital circuits formed of, for example, CMOSs or between the functional blocks using the same), and particularly to a fast bus transmission technology for high-speed data transfer through a bus between a plurality of LSIs connected on the same transmission line.
As a bus system for fast data transfer between a number of nodes as in the multiprocessor, there is an SSTL (Stub Series terminated Transceiver Logic) (EIA/JESD8-8) interface based on JEDEC (Joint Electron Device Engineering Council) standard. This interface, as shown in
FIG. 2
, is a bus system for use in transmission between LSIs that include input/output interfaces having receivers
21
~
25
for receiving data and drivers
11
~
15
for transmitting data. A data bus line (main line)
3
is terminated at both ends with a terminal resistor Rtt for matching so that the reflection at both ends can be removed. In addition, matching resistors
31
~
35
are respectively provided on stub lines
61
~
65
that connect the main line
3
and the interface circuits. The matching resistors
31
~
35
act to suppress the reflected waves due to impedance mismatching between the main line and the associated stub line when one of the drivers
11
~
15
transmits data.
In the SSTL interface shown in
FIG. 2
, however, a reflected wave due to impedance mismatching occurs on the signal waveform propagated on the main line
3
, disturbing high-speed operation. That is, for example, in
FIG. 2
, when data is transmitted from driver
11
to receiver
25
, the signal waveform from the driver
11
passes through the stub
61
and matching resistor
31
and arrives at the main line
3
. In general, the resistance value of the matching resistor
31
can be determined from the characteristic impedance Zo of stub
61
and the characteristic impedance Zo′ of main line
3
as given by the following equation (1).
Rm=Zo−Zo
′/2 (1)
where Rm is the matching resistance
31
. The equation (1) is the matching termination condition viewed from the stub side toward the main line. If the characteristic impedances Zo′, Zo of main line
3
and stub
61
are, for example,
50
&OHgr;, respectively, Rm is determined as 25&OHgr;=50−50/2.
On the other hand, the signal waveform transmitted from the driver
11
and arrived at the main line
3
further propagates to the left and right on the main line
3
. The waveform that progresses to the left terminates at the terminal resistor Rtt and thus there is no reflected wave. However, the signal to the right passes branch points
52
~
55
. The reflection coefficient &Ggr; at the branch point
52
is given by the following equation (2).
&Ggr;=(
Z
1
−
Zo
)/(
Z
1
+
Zo
) (2)
where Z
1
is the resultant impedance of the stub
62
including the main line
3
and matching resistor
32
, and given by the following equation (3).
Z
1
=(
Zo
′(
Rm+Zo
))/(
Zo′+Rm+Zo
)=30&OHgr; (3)
Thus, since the reflection coefficient &Ggr; is 0.25 at branch point
52
, 25% of the signal power is reflected at the point.
In other words, when the data from the driver
11
passes each of the branches on the main line
3
, 25% of the data is reflected at each branch and superimposed on the data. Since this reflected wave occurs during the round trip propagation delay of stub
61
~
65
, it is necessary to limit the stub line length in order that noise can be reduced for fast transmission. That is, a great restriction is imposed on the interface structure.
SUMMARY OF THE INVENTION
It is a first object of the invention to reduce the disturbances of impedance at these branch points, thereby decreasing the noise due to the reflected waves. Thus, it is possible to make much faster operation than SSTL.
It is a second object of the invention to reduce the restrictions on the stub line lengths from the LSI to each blanch point on the main line. Thus, it is possible to provide a greater freedom to the interface structure than SSTL.
It is a third object of the invention to incorporate the terminal resistors necessary for the high-speed bus within the LSIs instead of those on the main line, thereby reducing the mounting area.
The terminal resistors are built in the interface circuits of the LSIs so that the signals propagated on the stub lines can be prevented from being reflected from the interfaces. In addition, variable resistance elements are connected in series with the lines from each of the branch points on the main line. When the LSI receives data or does not transmit/receive data, the variable resistance element connected to the stub line with the LSI joined is made to be ⅓ of the characteristic impedance Zo of the line. When the LSI works as a driver, the variable resistance element connected through that stub line to the LSI is made to have a value of as low as about 5&OHgr; or below, the resistance element connected to the main line is set to have a low value, and the other resistance element is matched with the characteristic impedance Zo of the line.
Thus, when the LSI receives data or does not transmit/receive data, at the branch point, all lines appears to be completely matching-terminated since the resistance elements connected through the stub lines to the LSIs are set to be ⅓ of the characteristic impedance of the line. Therefore, since there is no reflection at the branch point, data can be transferred without noise.
In addition, when the LSI works as a driver, since the variable resistance element connected through the stub line to the LSI is set to have a value of as low as about 1&OHgr;, the element connected to the main line to have a low value and the other element to have the characteristic impedance of the line, about 80% of data can be propagated from the driver to the main line, and about 40% of the data, when transmitted to the other variable resistor, can be propagated with no reflection, thus the signal level being kept large enough.
REFERENCES:
patent: 5548226 (1996-08-01), Takekuma et al.
patent: 5568063 (1996-10-01), Takekuma et al.
patent: 5663661 (1997-09-01), Dillon et al.
patent: 5668834 (1997-09-01), Takekuma et al.
patent: 6125419 (2000-09-01), Umemura et al.
patent: 6188237 (2001-02-01), Suzuki et al.
patent: 6441639 (2002-08-01), Takekuma et al.
patent: 6515503 (2003-02-01), Griffin et al.
Ishibashi Kenichi
Osaka Hideki
Yamagiwa Akira
Antonelli Terry Stout & Kraus LLP
Hitachi , Ltd.
Myers Paul R.
Phan Raymond N
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