BPSG, SA-CVD liner/P-HDP gap fill

Details BPSG, SA-CVD liner/P-HDP gap fill BPSG, SA-CVD liner/P-HDP gap fill

2002-08-30

2003-09-02

Booth, Richard (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S594000, C438S595000

Reexamination Certificate

active

06613657

ABSTRACT:

FIELD OF THE INVENTION
Various issues arise in attempting to satisfy the ever increasing demands for miniaturization, particularly in fabricating non-volatile semiconductor devices, such as flash memory devices, e.g., electrically erasable programmable read only memory (EEPROM) devices. The demands for continuing miniaturization have led to the fabrication of flash memory devices comprising transistors having a gate width of about 0.18 micron and under and very closely spaced apart gate structures. In accordance with conventional practices, an oxide sidewall spacer is formed on side surfaces of the gate stack and a conformal silicon nitride layer, serving as an etch stop layer, is deposited over the gate structures including the sidewall spacers, thereby further reducing the gap between gate structures to about 0.125 micron or less. In accordance with conventional practices, a first interlayer dielectric (ILD
0
) is deposited over the gate structures and fills the gaps therebetween. Rapid thermal annealing is then conducted, as at a temperature of about 820° C. for about 120 seconds.
BACKGROUND ART
Various issues arise in attempting to satisfy the ever increasing demands for miniaturization, particularly in fabricating non-volatile semiconductor devices, such as flash memory devices, e.g., electrically erasable programmable read only memory (EEPROM) devices. The demands for continuing miniaturization have led to the fabrication of flash memory devices comprising transistors having a gate width of about 0.18 micron and under and very closely spaced apart gate structures. In accordance with conventional practices, an oxide sidewall spacer is formed on side surfaces of the gate stack and a conformal silicon nitride layer, serving as an etch stop layer, is deposited over the gate structures including the sidewall spacers, thereby further reducing the gap between gate structures to about 0.125 micron or less. In accordance with conventional practices, a first interlayer dielectric (ILD
0
) is deposited over the gate structures and fills the gaps therebetween. Rapid thermal annealing is then conducted, as at a temperature of about 820° C. for about 120 seconds.
As the distance between sidewall spacers of neighboring gate structures, after depositing the etch stop layer decreases to below about 0.125 micron, it becomes extremely difficult to fill the gaps with a gap fill oxide, even after post deposition rapid thermal annealing, without void formation. Such voiding in (ILD
0
) can lead to an open contact and shorting between contacts, thereby causing leakage and low production yields.
As miniaturization of flash technology proceeds apace, additional problems are encountered with respect to ILD
0
integrity as the aspect ratio of the gate stacks increases to about 3.0 and higher. It was found that undercutting of the sidewall spacers occurs, and even extends into the substrate surface. It is believed that such undercutting stems in part from undercutting of the oxide liner during wet cleaning with diluted hydrofluoric acid, such as hydrofluoric acid diluted with water at a level of 10:1 to 300:1, prior to metal deposition in implementing salicide technology. In addition, after silicidation, etching is conducted to remove unreacted metal remaining on the sidewall spacers, thereby attacking the silicon under the spacers, exacerbating the undercut regions. Attempts to deposit a phosphorous (P)-doped high density plasma (P-HDP) oxide layer as a gap fill layer have not been successful in filling these undercut regions, as such P-HDP oxide layers do not have sufficient fluidity. Consequently, the undercut regions remain as voids, thereby adversely impacting device reliability, as by facilitating boron penetration from the gate electrode through the gate oxide into the substrate, resulting in leakage upon rapid thermal annealing, as at a temperature of about 840° C. for about three minutes, during densification.
Accordingly, there exists a need for methodology enabling the fabrication of semiconductor devices, particularly flash memory devices, such as EEPROMs, with improved reliability. There exists a particular need for methodology enabling the fabrication of flash memory devices, such EEPROMs, with no or significantly reduced voids in the ILD
0
by enabling gap filling between neighboring transistors such that the undercut regions in sidewall spacers.
DISCLOSURE OF THE INVENTION
An advantage of the present invention is a method of manufacturing a semiconductor device exhibiting improved reliability.
Another advantage of the present invention is a method of manufacturing a flash memory semiconductor device with improved reliability.
A further advantage of the present invention is a method of manufacturing a flash memory device with reduced voids in the ILD
0
between closely spaced apart transistors and filled in undercut regions in sidewall spacers.
Another advantage of the present invention is a reliable semiconductor device having reduced leakage by virtue of oxide filled undercut regions in dielectric sidewall spacers on side surfaces of gate electrodes.
Additional advantages and other features of the present invention will be set forth in the description which follows and in part will be apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a method of manufacturing a semiconductor device, the method comprising: forming two gate electrode structures, spaced apart by a gap, on a semiconductor substrate; forming dielectric sidewall spacers on side surfaces of the gate electrode structures with undercut regions at the substrate; depositing a boron (B) and phosphorus (P)-doped sub-atmospheric-chemical vapor deposition (BPSG, SA-CVD) oxide liner having sufficient fluidity to flow into the undercut regions; flowing the B-HDP oxide liner into the undercut regions; and depositing a phosphorous (P)-doped high density plasma (P-HDP) oxide layer filling the gap.
Another advantage of the present invention is a semiconductor device comprising: two gate electrode structures, spaced apart by a gap, on a semiconductor substrate; dielectric sidewall spacers on side surfaces of the gate electrode structures, the dielectric sidewall spacers having undercut regions at the substrate; a boron (B) and phosphorus (P)-doped sub-atmospheric-chemical vapor deposition (BPSG, SA-CVD) oxide liner on the gate electrode structures and filling the undercut regions; and a phosphorous (P)-doped high density plasma (P-HDP) oxide layer filling the gap.
Embodiments of the present invention comprise forming silicon oxide spacers as the dielectric sidewall spacers and forming a silicon nitride liner over the silicon oxide sidewall spacers, wherein the silicon nitride liner extends into the undercut regions. Embodiments of the present invention include depositing the BPSG, SA-CVD oxide liner at a thickness of 1,000 Å to 1,800 Å at a low deposition rate of about 6 Å/second or less, rapid thermal annealing at a temperature of about 700° C. to about 1,000° C. e.g., about 840° C. for about 1 minute or at less than 840° C. for about 2 minutes, and then depositing the P-HDP oxide layer at a thickness of about 6,000 Å to about 10,000 Å at a deposition rate of at least 40 Å/second to fill the gap. Embodiments of the present invention further include depositing the BPSG, SA-CVD oxide liner containing 4.0 to 6.0 wt.% B for sufficient fluidity and containing 4.0 to 6.0 wt.% P for gettering purposes.
Additional advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description wherein embodiments of the present invention are described simply by way of illustration of the best mode contemplated for carrying out the present invention

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