Box isolation technique for integrated circuit structures

Details Box isolation technique for integrated circuit structures Box isolation technique for integrated circuit structures

1998-12-22

2000-06-13

Utech, Benjamin L.

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Total dielectric isolation

438423, 438480, 438528, 438691, 438694, 438766, H01L 21266

Patent

active

060749296

ABSTRACT:
A layer of silicon oxide is first formed on the silicon substrate. A mask is then formed on the oxide layer to define at least one surface region of the oxide that is not covered by the mask and a continuous strip of mask material that extends continuously around the unmasked oxide surface region. The mask is then used to etch the oxide surface region to expose an underlying substrate surface region and, thereby creating a continuous wall of oxide around the substrate surface region. The mask is then removed and oxygen ions are implanted into the silicon substrate to define a horizontal layer of oxide ions within the substrate. The wall of oxide surrounding the substrate surface region impairs the implant of oxygen ions beneath the wall such that a continuous substantially vertical wall of oxygen ions is formed in the substrate extending from the perimeter of the horizontal oxygen ion layer to the surface of the substrate. The substrate is then heat treated to cause the oxygen ions in the substrate to react with silicon to form silicon oxide that defines a silicon oxide island on all sides except the surface of the substrate, thereby forming an electrically isolated active device region.

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patent: 5422302 (1995-06-01), Yonehara et al.
patent: 5468657 (1995-11-01), Hsu
patent: 5930642 (1999-07-01), Moore et al.

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