Bottom gate mask ROM device

Details Bottom gate mask ROM device Bottom gate mask ROM device

1994-12-27

1996-07-23

Limanek, Robert P.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257391, 257 66, 257402, H01L 27112, H01L 2176

Patent

active

055392342

ABSTRACT:
A semiconductor device includes a semiconductor substrate doped with a first conductivity type. The substrate has a surface, with a parallel array of word lines ion implanted as regions in the surface of said substrate. The N+ word lines are of the opposite conductivity type from the P- substrate. A dielectric layer, formed on the substrate above the word lines, is covered with a polysilicon layer doped with a P- conductivity type. A second dielectric layer covers the polysilicon layer. A parallel array of N+ conductivity regions form doped N+ bit lines in the polysilicon layer. Above the N+ bit lines are formed alternating strips of planarized silicon nitride separated by silicon dioxide strips which are covered by a BPSG layer. An etched code pattern is formed extending through the polysilicon layer in a predetermined region providing an encoded RON.

REFERENCES:
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patent: 4364165 (1982-12-01), Dickman et al.
patent: 4365405 (1982-12-01), Dickman et al.
patent: 5002896 (1991-03-01), Naruke
patent: 5383149 (1995-01-01), Hong

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