Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2000-12-15
2003-01-28
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S653000, C438S656000
Reexamination Certificate
active
06511900
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to materials used during integrated circuit fabrication, and more particularly to materials used as diffusion barriers.
2. Background
A gate electrode is a structure commonly found in an integrated circuit. One fabrication technique of a gate electrode begins with the formation a gate oxide film on a semiconductor substrate. Following this step, a polysilicon layer is formed on the gate oxide film. A tungsten silicide layer is then deposited over the polysilicon layer using a chemical vapor deposition (CVD) process. The CVD process may include the use of a fluorine-containing gas, such as tungsten hexafluoride (WF
6
). Therefore, during CVD, fluorine atoms can be incorporated into the tungsten suicide layer.
Once the gate oxide film, the polysilicon layer, and the tungsten silicide layer have been formed on the substrate, the device is annealed. During this anneal, fluorine atoms undesirably diffuse from the tungsten suicide layer through the polysilicon layer to the gate oxide film.
To reduce the diffusion of fluorine atoms during the anneal, attempts have been made to incorporate a diffusion barrier layer under the tungsten silicide layer during the fabrication of gate electrodes. Conductive diffusion barrier layers comprise materials such as titanium nitride, titanium tungsten, or tantalum nitride. Although these materials inhibit fluorine diffusion to some extent, they still allow a substantial amount of fluorine to diffuse from the metal layer to the gate oxide film.
When fluorine atoms diffuse to the gate oxide film, they react with the gate oxide film in a manner that increases its electrical thickness. Furthermore, fluorine diffusion can lower breakdown voltage and increase defect density. Fluorine diffusion can also cause device degradation, such as a shift in threshold voltage or a decrease in saturation current.
SUMMARY OF THE INVENTION
A diffusion barrier layer comprising TiN
x
B
y
is disclosed for protection of gate oxide layers in integrated transistors. The diffusion barrier layer can be fabricated by first forming a TiN layer and then incorporating boron into the TiN layer. The diffusion barrier layer can also be fabricated by forming a TiN
x
B
y
layer using a TDMAT process including boron. The diffusion barrier layer can also be fabricated by forming a TiN
x
B
y
layer using a CVD process. The diffusion barrier layer is of particular utility in conjunction with tungsten or tungsten silicide conductive layers formed by CVD.
One embodiment of the invention relates a gate electrode of an integrated circuit which comprises a gate oxide layer and a polysilicon layer formed over the gate oxide layer. The gate electrode further comprises a tungsten layer formed over the polysilicon layer. The gate electrode also comprises a diffusion barrier layer formed between the polysilicon layer and the tungsten layer, wherein the diffusion barrier layer comprises TiN
x
B
y
.
Another embodiment of the invention relates to an integrated circuit structure that comprises a dielectric layer and a conductive layer above the dielectric layer. The conductive layer has at least some fluorine atoms therein. The integrated circuit structure further comprises a TiN
x
B
y
barrier layer between the conductive layer and the dielectric layer, wherein the TiN
x
B
y
barrier layer inhibits the amount of the fluorine atoms which diffuse into the dielectric layer.
An additional embodiment of the invention relates to a gate in an integrated circuit that comprises a dielectric layer and a TiN
x
B
y
layer formed over at least a portion of the dielectric layer. The gate further comprises a tungsten layer formed over at least a portion of the TiN
x
B
y
layer.
One embodiment of the invention relates to an integrated circuit structure that comprises a TiN
x
B
y
layer and a chemical vapor deposition conductive layer overlying the TiN
x
B
y
layer. Yet another embodiment of the invention relates to an integrated circuit structure that comprises a TiN
x
B
y
layer and a tungsten layer overlying the TiN
x
B
y
layer.
Another aspect of the invention relates to a method of forming a gate electrode comprising the act of forming a gate oxide layer over a semiconductor substrate. The method further comprises the act of forming a TiN
x
B
y
layer over at least a portion of the gate oxide layer. The method also comprises the act of forming a tungsten layer over at least a portion of the TiN
x
B
y
layer.
An additional aspect of the invention relates to a method of forming an integrated circuit structure. The method comprises the act of forming a dielectric layer. The method further comprises the act of combining tetrakisdimethyl-aminotitanium (TDMAT) with a boron containing source gas to form a diffusion barrier over at least a portion of the dielectric layer.
Yet another aspect of the invention relates to a method of forming an integrated circuit structure. The method comprises the act of forming a dielectric layer. The method further comprises the act of forming a TiN
x
B
y
layer over at least a portion of the dielectric layer. The method also comprises the act of forming a conductive layer over at least a portion of the TiN
x
B
y
layer by combing tungsten hexafluoride and silicon tetrahydride.
A further aspect of the invention relates to a method of forming a gate electrode on a substrate. The method comprises the acts of forming a gate oxide layer over a substrate and forming a TiN layer between the gate oxide layer and the conductive layer. The method further comprises the act of incorporating boron into the TiN layer to form a barrier layer. The method also comprises the act of forming a tungsten layer over at least a portion of the barrier layer.
One embodiment of the invention relates to a method of forming an integrated circuit structure. The method comprises the acts of forming a dielectric layer and forming a barrier layer over the dielectric layer. The method also comprises the act of forming a conductor layer above the dielectric layer wherein the conductor layer releases fluorine atoms. The method further comprises the act of inhibiting at least a portion of the fluorine atoms from diffusing into the dielectric layer.
For purposes of summarizing the invention, certain aspects, advantages and novel features of the invention are described herein. It is to be understood that not necessarily all such advantages may be achieved in accordance with any particular embodiment of the invention. Thus, for example, those skilled in the art will recognize that the invention may be embodied or carried out in a manner that achieves one advantage or group of advantages as taught herein without necessarily achieving other advantages as may be taught or suggested herein.
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Baker, et al., “Combined X-Ray Photoelectron/Auger
Agarwal Vishnu K.
Sandhu Gurtej S.
Knobbe Martens Olson & Bear LLP
Lindsay Jr. Walter L.
Micro)n Technology, Inc.
Niebling John F.
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