Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having schottky gate
Reexamination Certificate
2001-02-05
2002-04-30
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having schottky gate
C438S194000, C438S230000
Reexamination Certificate
active
06380012
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 89126180, filed Dec. 8, 2000.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method of manufacturing a semiconductor device. More particularly, the present invention relates to a boron difluoride plasma doping method for forming an ultra-shallow junction.
2. Description of Related Art
As gate width of a metal-oxide-semiconductor (MOS) device drops to 0.18 &mgr;m or smaller, the channel length of the MOS device also reduces correspondingly. Hence, junction depth of the source/drain terminal must be controlled precisely in order to reduce punchthrough current and short channel effect. Ultimately, the fabrication of an ultra-shallow junction in the substrate is essential. To produce a small dimensional semiconductor device, a lower energy implantation has to be conducted to reduce implant depth. Moreover, a faster thermal annealing operation is required to prevent the diffusion of the implanted dopants.
At present, methods for forming an ultra-shallow junction include ultra-low energy ion implantation, wafer tilt implantation and pre-amorphized implantation. In general, the ultra-low energy ion implantation is unsuitable for fabricating semiconductor devices having a line width smaller than 0.1 &mgr;m. This is because the ions produced in an ultra-low ion implantation have very low speed. With an ion flow rate of only about one-tenth of the previous generation, a long implantation period is required. Hence, production rate is too low for mass production. On the other hand, as channel length of a semiconductor device continues to reduce, wafer tilt implantation will produce source/drain terminals that extend deep into the region underneath the gate. Consequently, punch-through and short channel effect will be intensified. Furthermore, since low energy is already used in the implantation of most small dimensional devices, ultra shallower junction can no longer be obtained from pre-amorphized implantation.
In addition, the cross-section of the ion beam used in a conventional ion implantation method is generally very narrow. A two-dimension scanning of the ion beam across the surface of a wafer is often required to implant ions into every region of a wafer. Therefore, a lot of time is required to produce each wafer.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide a boron difluoride plasma doping method to form an ultra-shallow junction such as a PMOS ultra-shallow junction. First, a semiconductor substrate is put inside a reaction chamber and then a boron difluoride ions (BF
2
+
) containing plasma is generated inside the chamber. A negative voltage is applied to the semiconductor substrate so that the boron difluoride ions (BF
2
+
) accelerate and bombard against the semiconductor substrate to form an ultra-shallow junction on a superficial layer of the substrate. Finally, a rapid annealing operation is conducted to repair any defects in the crystal lattice that results from the formation of the ultra-shallow junction.
According to the method of this invention, a wafer is placed inside a reaction chamber and then boron difluoride plasma is generated inside the reaction chamber so that the entire wafer is surrounded by boron difluoride ions (BF
2
+
). With the application of a suitable size negative voltage to the semiconductor substrate, boron difluoride ions (BF
2
+
) are implanted into the substrate to form an ultra-shallow junction. Thus, this invention can be regarded as a high ion flow rate global ion implantation. Unlike a conventional low-ion-flow-rate low-energy-level ion beam implantation, less time is required to produce each wafer and productivity can be increased.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 6107129 (2000-08-01), Gardner et al.
patent: 6127216 (2000-10-01), Yu
patent: 6225176 (2001-05-01), Yu
J.C. Patents
Le Thao P
Macronix International Co. Ltd.
Nelms David
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