Borderless vias

Details Borderless vias Borderless vias

1999-03-02

2001-05-15

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S638000, C438S639000, C438S644000, C438S645000, C438S648000, C438S654000, C438S622000, C438S788000, C257S750000, C257S758000, C257S753000, C257S752000, C257S751000

Reexamination Certificate

active

06232221

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a method of manufacturing a high density, multi-metal layer semiconductor device exhibiting a reliable interconnection pattern. The invention has particular applicability in manufacturing high density multi-metal layer semiconductor devices with design features of 0.25 micron and under.
BACKGROUND ART
The escalating requirements for high densification and performance associated with ultra large scale integration semiconductor devices require design features of 0.25 micron and under, such as 0.18 microns, increased transistor and circuit speeds, high reliability, and increased manufacturing throughput. The reduction of design features to 0.25 microns and under generates numerous problems challenging the capabilities of conventional interconnection technology, including conventional photolithographic, etching, and deposition techniques.
Conventional methodology for forming patterned metal layers comprises a subtractive etching or etch back step as the primary metal patterning technique. Such a method involves the formation of a first dielectric layer on a semiconductor substrate, typically monocrystalline silicon, with conductive contacts formed therein for electrical connection with an active region on the semiconductor substrate, such as a source/drain region. A metal layer, such as aluminum or an aluminum alloy, is deposited on the first dielectric layer, and a photoresist mask is formed on the metal layer having a pattern corresponding to a desired conductive pattern. The metal layer is then etched through the photoresist mask to form the conductive pattern comprising metal features separated by gaps, such as a plurality of metal lines with interwiring spacings therebetween. A dielectric layer, such as spin-on-glass (SOG) or high density plasma (HDP) oxide, is then applied to the resulting conductive pattern to fill in the gaps and the surface is planarized, as by conventional etching or chemical-mechanical polishing (CMP) planarization techniques.
As feature sizes, e.g., metal lines and interwiring spacings, shrink to 0.25 micron and below, such as 0.18 micron, it becomes increasingly difficult to satisfactorily fill in the interwiring spacings voidlessly and obtain adequate step coverage. It also becomes increasingly difficult to form a reliable interconnection structure. A through-hole is typically formed in a dielectric layer to expose an underlying metal feature, wherein the metal feature serves as a landing pad occupying the entire bottom of the through-hole. Upon filling the through-hole with conductive material, such as a metal plug to form a conductive via, the entire bottom surface of the conductive via is in direct contact with the metal feature.
A conventional conductive via is illustrated in
FIG. 1
, wherein first metal feature
10
of a first patterned metal layer is formed on first dielectric layer
11
and exposed by through-hole
12
formed in second dielectric layer
13
. First metal feature
10
is typically formed as a composite structure comprising a lower metal layer
10
A, e.g., titanium (Ti) or tungsten (W), an intermediate or primary conductive layer
10
B, e.g., aluminum (Al) or an Al alloy, and an anti-reflective coating (ARC)
10
C, such as titanium nitride (TiN). In accordance with conventional practices, through-hole
12
is formed so that first metal feature
10
encloses the entire bottom opening, thereby serving as a landing pad for the metal plug filling through-hole
12
to form the conductive via. Thus, the entire bottom surface of conductive via
16
is in direct contact with first metal feature
10
.
Conductive via
16
electrically connects first metal feature
10
and second metal feature
14
which is part of a second patterned metal layer. Second metal feature
14
is also typically formed as a composite structure comprising lower metal layer
14
A, primary conductive layer
14
B and ARC
14
C. The plug filling the through-hole to form the conductive via is typically formed as a composite comprising a first adhesion promoting layer
15
, which is typically a refractory material, such as TiN, Ti—W, or Ti—TiN, and a primary plug filling metal
17
such as W. Metal features
10
and
14
typically comprise metal lines with interwiring spacings therebetween conventionally filled with dielectric material
18
, such as SOG or HDP oxide. The reduction in design features to the range of 0.25 micron and under requires extremely high densification which mandates high aspect ratio (height/diameter) openings. As the aspect ratio of openings increases, it becomes increasingly more difficult to deposit a barrier layer
15
(
FIG. 1
) by conventional sputtering techniques.
The conventional practice of forming a landing pad completely enclosing the bottom surface of a conductive via utilizes a significant amount of precious real estate on a semiconductor chip which is antithetic to the escalating high densification requirements. In addition, it is extremely difficult to voidlessly fill through-holes having such reduced dimensions because of the extremely high aspect ratio, e.g., in excess of 4. Accordingly, conventional remedial techniques comprise purposely widening the diameter of the through-hole to decrease the aspect ratio. As a result, misalignment occurs wherein the bottom surface of the conductive via is not completely enclosed by the underlying metal feature, but extends off of the metal feature onto surrounding dielectric material. This type of via is called a “borderless via”, which also conserves chip real estate.
The use of borderless vias, however, creates new problems. For example, as a result of misalignment, the SOG gap filling layer is penetrated during etching to form a misaligned through-hole, due to the low density and poor stability of SOG. As a result of such penetration, moisture and gas accumulate, thereby increasing the resistance of the interconnection. Spiking can also occur, i.e., penetration of the metal plug to the substrate causing a short. Even without complete penetration, a side surface of the lower metal feature is exposed in forming a misaligned through-hole. Upon filling the misaligned through-hole with W employing vaporous tungsten hexafluoride (WF
6
), an undesirable interaction with Al occurs.
For example, adverting to
FIG. 2
, first metal feature
22
is formed on substrate
21
. Metal feature
22
is typically a composite comprising lower metal layer
22
A, such as Ti or W, primary conductive layer
22
B, e.g., Al or an Al-alloy, and ARC
22
C, such as titanium nitride. Upon etching dielectric interlayer
23
to form misaligned through-hole
24
, a side surface of lower metal feature
22
is exposed, as indicated by reference numeral
25
. Upon subsequent deposition of W utilizing WF
6
, an undesirable interaction occurs.
In U.S. Pat. No. 5,619,072, methodology is disclosed for preventing spiking, which methodology includes the formation of sidewall spacers on the side surfaces of the lower metal feature, which sidewall spacers serve as an etch stop layer when etching the misaligned through-hole. The dielectric interlayer comprises a material different from the sidewall spacer material, and an etchant is chosen which exhibits a greater selectivity with respect to the sidewall spacer material. However, etch selectivity is not infinite and, invariably, a portion of the upper surface of the sidewall spacer is removed, leaving exposed a portion of the primary conductive layer, i.e., Al or an Al-alloy.
For example, adverting to
FIG. 3
, metal feature
31
, a composite comprising lower metal layer
31
A, a primary conductive layer
31
B containing Al or an Al-alloy, and ARC
32
C, is formed on substrate
30
. Sidewall spacers
33
A and
33
B are formed with the side surfaces of lower metal feature
31
extending to the upper surface thereof. Dielectric interlayer
34
is deposited and misaligned through-hole
35
formed therein. As etch selectivity is not infinite, an upper portion of sidewall spacer
33
B (indicated by dotted line
36
) is removed, leaving exp

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