Borderless master slice CMOS device

Details Borderless master slice CMOS device Borderless master slice CMOS device

1989-05-25

1990-07-17

Munson, Gene M.

357 41, H01L 2702

Patent

active

049424475

ABSTRACT:
A borderless master slice semiconductor device is disclosed which comprises a plurality of first conduction type well regions arranged in a matrix type on the whole face of a second conduction type wafer; a plurality of second conduction type MOS transistor groups; a plurality of first conduction type diffusion regions arranged alterntely with the said second conduction type MOS transistor groups on the same row; a plurality of first conduction type MOS transistor groups arranged in a row direction facing opposingly with said second conduction type MOS transistor groups; and a plurality of second conduction type diffusion regions arranged alternately with said first conduction type MOS transistor groups on the same row. The device of the present invention thus constituted will bring the result that the master chip can be designed arbitrarily upon to the optimum size correspondingly with customer's order and that the production process can be singularized and the product control can be simplified.

REFERENCES:
patent: 4644382 (1987-02-01), Charransol et al.
patent: 4682202 (1987-07-01), Tanizawa
patent: 4724531 (1988-02-01), Angleton et al.
patent: 4766475 (1988-08-01), Kawashima
patent: 4771327 (1988-09-01), Usui

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