Borderless contact to diffusion with respect to gate...

Details Borderless contact to diffusion with respect to gate... Borderless contact to diffusion with respect to gate...

1998-05-12

2001-04-10

Lee, Eddie C. (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

C257S640000, C257S649000

Reexamination Certificate

active

06215190

ABSTRACT:

DESCRIPTION
1. Technical Field
The present invention is concerned with providing a borderless contact to diffusion with respect to the gate conductor. The present invention permits the diffusion contact to overlap the gate conductor without shorting to the gate. In particular, the present invention is concerned with methods to provide a borderless contact to diffusion and gate conductor employing a single contact mask step. In addition, the present invention is concerned with a semiconductor structure having the desired borderless contact. The present invention is especially applicable for fabricating SRAM cells and logic with embedded SRAM.
2. Background of Invention
In the formation of semiconductor devices, it is necessary to provide both desired electrical contact between certain regions of the devices formed and also to prevent contact between various other regions of the devices formed on the substrate. One technique for accomplishing this has been by using photoresist and masking techniques wherein those areas to be exposed for electrical contact are patterned in the photoresist, and then by developing the patterned photoresist, to thereby expose the desired underlying regions. This technique normally requires several successive masks to perform the entire process, and in its performance each succeeding mask must be precisely aligned. However, as the technology advances, allowing for formation of smaller and smaller devices, it is increasingly difficult to maintain precise overlay tolerance, with the result that even small misalignments of the masks will result in the exposure of small portions or “borders” of regions that are intended to remain covered. Hence, electrical connections, e.g. by an overlay deposition of a metal, will connect not only the desired locations, but also those exposed border portions of the undesired locations.
In view of this, what has been referred to as borderless contacts have been fabricated. However, in the case of for instance SRAM cells, a limiting factor for shrinking the cells is the contact to diffusion with respect to gate-conductor. This limiting factor ensures that the diffusion contact does not short to the gate conductor. This has been achieved by simply providing ample distance between the diffusion contacting gate such that the contact never intersects the gate within the process tolerances employed. Borderless contact allows the intersection of a contact to a “border” in the case of a SRAM cell being the gate, by providing means to prevent electrical shorts if the contact intersects the border, thereby permitting the distance between the border and the contact to be reduced. In addition, in a borderless contact it is necessary to contact the borderless element itself such as in the case of a SRAM cell permit contact to the gate conductor. To accomplish this, a separate gate contact mass has previously been used, but this adds another critical mask step. Accordingly, it would be desirable to provide a method for achieving a borderless contact to diffusion and gate contact that does not cause shorting and does not require additional masking steps.
SUMMARY OF INVENTION
The present invention is concerned with providing a borderless contact to diffusion with respect to gate conductor. In particular, according to the present invention, borderless contact is achieved while guarding against shorting. Moreover, according to a preferred aspect of the present invention a borderless contact is achieved employing a single contact mask.
More particularly, the present invention is concerned with a semiconductor structure that comprises a semiconductor substrate; a conductive region on the substrate; borderless contacts adjacent the conductive regions; and the conductive regions having intermittent self-aligned insulating caps for protecting the borderless contacts, and having capless area s for contacting the conductive regions.
In addition, the present invention is concerned with a method for fabricating such a semiconductor structure. In particular, the process of the present invention comprises providing a semiconductor substrate; providing a first insulating layer on the semiconductive substrate and forming a conductive layer on the first insulating layer. A second insulating layer is formed on the conductive layer and a third insulating layer is formed on the second insulating layer. Next, the process involves selectively removing a portion of the second and third insulating layers in a predetermined pattern and then forming a damage prevention layer where the second and third insulating layers were removed. The damage prevention layer is a self-aligned layer formed by oxidation of the conductive layer to permit removal of the third insulating layer. Preselected portions of the remaining third insulating layer is selectively removed in a predetermined pattern followed by removing the damage prevention layer without etching the conductive layer. The exposed portions of the conductive layer uncovered by the second insulating layer is now removed. The second insulating layer exposed by the removal of the third insulating layer is removed to thereby provide the desired semiconductor structure.
According to a further aspect of the present invention, an alternative method for fabricating structures with borderless contact to diffusion with respect to gate conductor is provided. This alternative process includes providing defined conductive gate structure on semiconductor substrate and blanket depositing a barrier layer followed by blanket depositing a first insulating layer. The first insulating layer is polished with the gate stack of the barrier layer and gate acting as the polish stop thereby exposing the top of the gate. Selected portions of the barrier layer and underlying gate portions are etched to correspond to those areas to be subsequently isolated from contacts to the diffusion. A conformal barrier layer is then deposited followed by a polysilicon layer for filling the recesses created in the gate regions. The polysilicon is polished stopping on the barrier layer. Exposed barrier layer is removed and a second insulating layer is deposited. This creates the material for forming contacts to the diffusion and gates in the areas not covered with the isolation cap.
In a still further embodiment of the present invention, fabrication of the desired structure is achieved by providing conductive gate on a semiconductor substrate, blanket depositing a barrier layer over the gate and substrate, and blanket depositing a non-conformal first insulating layer over the barrier layer. The non-conformal layer is thicker on the horizontal surfaces as compared to the vertical sidewalls of the gate structure. A sacrificial metallic layer is deposited and selectively polished so that the polish will stop on the protruding insulating peaks on top of the conductive gate lines. The insulating layer is etched with the etch stopping on the underlying barrier layer. Recess areas in the insulating layer above the gate regions which are to receive a protective cap are filled and planarized with the tops of the remaining portions of the sacrificial layer. The sacrificial layer is then removed thereby leaving a cap on top of the gate regions that will act as an etch stop and insulating material for subsequent etching and filling to provide the self aligned contact. The structure is then covered with a second insulating layer which can then be planarized. The structure is then patterned and etched with contacts to diffusion that are borderless to the already capped conductive gate lines. Those areas of the conductive gates lines that are not capped are capable of being contacted with the same etch used in the patterning for the diffusion contacts.
A still further embodiment of the present invention comprises blanket depositing a barrier layer over preformed gate and over semiconductor substrate and then depositing a first insulating layer over the barrier layer. The insulating layer is planarized and the structure is masked so that open regions correspond to wher

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