Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Patent
1998-07-13
2000-07-04
Niebling, John F.
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
438631, 438633, 438638, 438639, 438666, 438672, 438687, H01L 214763
Patent
active
060838248
ABSTRACT:
A method of forming borderless contacts and vias is disclosed. Borders which are conventionally provided in aligning contacts and vias to device and/or metal regions in a semiconductor device take up too much valuable real estate on semiconductor substrates, and hence reduce productivity of the products. By employing a hard-mask of this invention, and a specific sequence of process steps, alignment can be achieved without the need for borders. First, a thin nitride layer is deposited on an insulating layer formed over a substructure of a substrate having device and/or metal regions. The hard-mask is patterned with metal line openings, and a photoresist layer is formed with contact or via pattern over the already patterned hard-mask. The contact/via openings are etched into the dielectric layer until the substructure is reached. The hole openings are filled plug metal and then partially etched back, leaving a plug in the hole opening. The line trench is etched further into the dielectric layer until metal plug is reached. The trench is then filled with metal, such as aluminum-copper or copper and the excess is removed by chemical-mechanical polishing. Thus, a borderless and self-aligned interconnect comprising plug and metal line is formed.
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Ho Chin-Hsiung
Sun Yuan-Chen
Tsai Chao-Chieh
Ackerman Stephen B.
Gurley Lynn A.
Niebling John F.
Saile George O.
Taiwan Semiconductor Manufacturing Company
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