Borderless bitline and wordline DRAM structure

Details Borderless bitline and wordline DRAM structure Borderless bitline and wordline DRAM structure

2000-09-08

2002-07-16

Prenty, Mark V. (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S773000

Reexamination Certificate

active

06420748

ABSTRACT:

FIELD OF INVENTION
This invention relates generally to DRAM cell design using transistors and semiconductor interconnection techniques, and more particularly to a conductive wordline for a DRAM cell and a method of making the same wherein the bitline contact is borderless to the wordline which is especially useful in folded-bitline architecture for DRAMS.
BACKGROUND OF THE INVENTION
Large numbers of DRAM cells must be interconnected with wordlines, and wordlines and spaces between wordlines are determinative of the size of a folded-bitline cell. Typically, wordlines are formed as thin films of a conductor, such as aluminum or polysilicon, deposited on insulating materials on the semiconductor surface and defined as lines photolithographically. Efforts to shrink wordlines and the spaces between wordlines are limited since both line widths and spaces cannot lithographically be made smaller than the minimum photolithographically defined line. While it is possible to decrease the line width, for example, decreasing the line width usually increases the line-to-line spacing and so the overall wordline pitch is not improved. The cost of decreasing the photolithographic minimum dimension is high, and each such effort has defined succeeding generations of semiconductor products. In each generation of DRAM cells, the photolithographically defined wordline and it's associated space have each thus been formed at the photolithographic minimum. Each such effort has defined succeeding generations of semiconductor products. As the capacitor, transfer device, and associated isolators continue to shrink past the wiring 8 squares limit, the lithographically formed planar wiring will limit the ultimate DRAM cell size. A one device and one capacitors folded DRAM cell is comprised of three discrete connections (wires) and a capacitor plate. The three wires is include two wordlines and one bitline or one wordline and two bitlines. The packing of the wires is one of the main determinants of the DRAM cell size.
In the folded-bitline DRAM cell design, both an active and a passing wordline pass through each cell, as illustrated in commonly assigned U.S. Pat. No. 4,801,988 (“the '988 patent”), issued to D. M. Kenney, entitled “Semiconductor Trench Capacitor Cell with Merged Isolation and Node Trench Construction,” and shown therein which is incorporated herein by reference. Crossing over trench capacitors
505
A and
510
A for a pair of cells in
FIG. 1
, are wordlines
515
A and
520
A. The space required for such a DRAM cell is a minimum dimension for each of the two wordlines in each cell and an additional minimum dimension for each space between each wordline. Thus the total minimum length of the traditional cell is 4 minimum dimensions. The width of the cell is at least two minimum dimensions, of which one is for the components in the cell and the other is for a thick isolation (a trench capacitor can be a part of this isolation) as well as for the bitline connector between bitlines and in the space between cells. Thus, the minimum area of a traditional DRAM cell has been 8 square minimum dimensions, or 8 squares.
One approach to avoid the photolithographic limit is to provide a wordline formed of a conductive sidewall rail. The width of such rails is determined by the thickness of the deposited conductor, and this thickness can be significantly less than a minimum photolithographic dimension. Commonly assigned U.S. Pat. No. 5,202,272 (“the '272 patent ”), issued to Hsieh, entitled “Field Effect Transistor Formed With Deep-Submicron Gate,” and U.S. Pat. 5,013,680 (“the '680 patent”), issued to Lowrey, entitled “Process for Fabricating a DRAM Array Having Feature Widths that Transcend the Resolution Limit of Available Photolithography,” all of which are incorporated herein by reference, teach methods of using a subminimum dimension conductive sidewall spacer rail to form a wordline.
One problem encountered in the use of such subminimum dimension spacer rail wordlines is the difficulty of precisely controlling the length of the device and the extent of lateral diffusion of the source and drain. For example, small variations of spacer thickness or lateral diffusion can result in a large variation in the length of the subminimum dimension channel. The result can be large leakage currents on the one hand and degraded performance on the other. The present invention avoids the difficulties of the subminimum dimension sidewall spacer rail wordlines of the prior art.
Moreover, prior art structures and techniques for sublithographic wordlines and/or bitlines do not provide the bitline contact being borderless to the wordline.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a folded-bitline DRAMA cell with a photolithographically formed gate, the cell having an area of less than 8 squares with the bitline contact being borderless to the wordline.
It is also a feature of the present invention that a subminimum dimension wordline links approximately minimum dimensional individual gate segments with the bitline contact being borderless to the wordline.
It is still a further object of the present invention to provide a transistor with an individual segment gate conductor and a subminimum dimension gate connector with the bitline contact being borderless to the wordline.
These and other objects of the invention are accomplished by semiconductor structure comprising a DRAM cell which has a transistor which includes a gate. The gate comprises an individual segment of gate conductor such as polysilicon on a thin dielectric material. The transistor further comprises a single crystal semiconductor substrate having a source/drain region. An active conductive wordline is deposited on top of and electrically contacting the segment gate conductor with the wordline being a conductive material. Insulating material completely surrounds the wordline except where the wordline contacts the segment gate conductor. A bitline contact contacting the insulating material surrounds the wordline contact in the source/drain region to thereby make the bitline contact borderless to the wordline. The present invention also provides a method of making such a DRAM cell.


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