Booting mechanism for FPGA-based embedded system

Details Booting mechanism for FPGA-based embedded system Booting mechanism for FPGA-based embedded system

2006-03-10

2010-10-26

Tran, Vincent T (Department: 2115)

Electrical computers and digital processing systems: support

Digital data processing system initialization or configuration

C711S154000, C326S041000

Reexamination Certificate

active

07822958

ABSTRACT:
According to various embodiments of the present invention, a programmable device assembly includes an FPGA coupled to a nonvolatile serial configuration memory (e.g., serial flash memory) and a volatile fast bulk memory (e.g., SRAM or SDRAM). The nonvolatile serial configuration memory contains both the FPGA configuration data and CPU instructions. When a predetermined condition occurs, a serial memory access component that is hard coded on the FPGA automatically reads the configuration data from the nonvolatile serial configuration memory. The configuration data is used to configure the FPGA with various components, including a CPU, a boot ROM with code for a boot copier, and a bus structure. When the CPU boots, code for the boot copier is executed so that the CPU instructions are copied from the nonvolatile serial configuration memory to the volatile fast bulk memory. The CPU then executes the CPU instructions stored in the volatile fast bulk memory.

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Nios II Flash Promarammer User Guide, Copyright @2004 Altera Corporation.

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