Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
2006-07-19
2009-02-24
Nguyen, Hiep T (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
Reexamination Certificate
active
07496708
ABSTRACT:
Embodiments of the invention address deficiencies of the art in respect to boot ROM handling and provide a method, system and computer program product for optimized boot ROM handling for I/O devices. In one embodiment of the invention, a ROM scan area optimization method can be provided. The method can include pre-processing multiple boot ROM images to determine memory space requirements in the ROM scan area for all of the boot ROM images. The method further can include partitioning the ROM scan area into multiple, different static portions and at least one dynamic paged portion. Finally, the method can include generating an optimal arrangement of the boot ROM images defining placement of some of the boot ROM images in corresponding ones of the static portions, and others of the boot ROM images in the dynamic paged portion.
REFERENCES:
patent: 7284084 (2007-10-01), Atherton et al.
patent: 2003/0159025 (2003-08-01), Dubal
Atherton William E.
Dayan Richard A.
Dunham Scott N.
Schwartz William B.
Byrd, Esq. Cynthia S.
Cary Rodriguez Greenberg & Paul LLP
Greenberg, Esq. Steven M.
International Business Machines - Corporation
Nguyen Hiep T
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