Boosting voltage level detector for a semiconductor memory devic

Details Boosting voltage level detector for a semiconductor memory devic Boosting voltage level detector for a semiconductor memory devic

1994-11-18

1998-04-21

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

327535, G05F 110

Patent

active

057421978

ABSTRACT:
A boosting voltage level detector for a semiconductor memory device which utilizes a boosting voltage the level of which is higher than that of a power supply voltage, which includes a pull-up portion and a pull-down portion. In a preferred embodiment, the pull-up portion includes a PMOS transistor and a first NMOS transistor connected in series between the power supply voltage and an output node, and the pull-down portion includes second and third NMOS transistors connected in series between the output node and ground. The PMOS transistor has a gate electrode which is coupled to ground, and thus functions as a current source. The second NMOS transistor has a gate electrode which is coupled to a reference voltage, and thus functions as a resistor. The gate electrodes of the first and third NMOS transistors are commonly coupled to the boosting voltage. The detector further includes an inverter circuit coupled to the output node. The voltage value of the output node rises above the trip point level of the inverter in response to the boosting voltage rising above a predetermined voltage level, and the voltage value of the output node falls below the trip point level in response to the boosting voltage falling below the predetermined voltage level.

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