Boosting clamping circuit and output buffer circuit using the sa

Details Boosting clamping circuit and output buffer circuit using the sa Boosting clamping circuit and output buffer circuit using the sa

1992-04-30

1993-12-07

Hudspeth, David R.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307556, 307578, H03K 458

Patent

active

052686000

ABSTRACT:
A boosting-clamping circuit for initially outputting a boosted voltage level, and lowering and clamping the output voltage level to a predetermined level as time elapses, and an output buffer circuit using the same, includes a boosting circuit for receiving a signal to boost and outputting the signal into a high input impedance device and a clamping circuit having one node connected to the output terminal of the boosting circuit and the other node connected to ground, for lowering and clamping the output voltage level of the boosting circuit to a predetermined level as time elapses. The output buffer circuit using the boosting-clamping circuit has a fast response time and a proper output voltage level when outputting a data bit "1," thereby reducing the ground noise during outputting data "0" and improving the response speed of data "0".

REFERENCES:
patent: 4508978 (1985-04-01), Reddy
patent: 4527077 (1985-07-01), Higuchi et al.
patent: 4570244 (1986-02-01), Sud et al.
patent: 5027013 (1991-06-01), Coy et al.

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