Boosting circuit using 2-step boosting operation

Details Boosting circuit using 2-step boosting operation Boosting circuit using 2-step boosting operation

1999-10-04

2000-10-24

Elms, Richard

Static information storage and retrieval

Read/write circuit

Including reference or bias voltage generator

365226, G11C 1604

Patent

active

061377333

ABSTRACT:
A semiconductor memory device with a boosting circuit includes a first power supply line, a second power supply line supplying a power supply potential, first and second boosting capacitors connected to the first power supply line, and a control circuit. The control circuit connects the second power supply line to the first power supply line for a first time interval such that the first power supply line and the first and second boosting capacitors, boosts the first power supply line and the second boosting capacitor by the first boosting capacitor for a second time interval after the first time interval, and boosts the first power supply line by the second boosting capacitor for a third time interval after the second time interval.

REFERENCES:
patent: 5406523 (1995-04-01), Foss et al.
patent: 5623446 (1997-04-01), Hisada et al.
patent: 5828620 (1998-10-01), Foss et al.
patent: 5940333 (1999-08-01), Chung

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