Boosting circuit of semiconductor memory device

Details Boosting circuit of semiconductor memory device Boosting circuit of semiconductor memory device

2000-07-27

2003-09-02

Zweizig, Jeffrey (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

Reexamination Certificate

active

06614292

ABSTRACT:

This application claims priority from Korean Patent Application No. 1999-30871, filed on Jul. 28, 1999, the contents of which are herein incorporated by reference in their entirety.
FIELD OF THE INVENTION
The present invention relates generally to a semiconductor memory device. More specifically, the present invention is directed to a boosting circuit of a semiconductor memory device.
BACKGROUND OF THE INVENTION
Referring to
FIGS. 1 and 2
, a conventional flash memory cell
1
comprises a current path or channel region
5
formed between a source
3
and a drain
4
on a semiconductor substrate
2
. A floating gate
6
is formed on the substrate
2
between insulating layers
7
and
9
, and has a predetermined thickness (e.g., approximately 100 Å). A control gate
8
is formed above the floating gate
6
.
TABLE 1
Operation Mode
Vg
Vd
Vs
Vb
Program
+10V
+5V~+6V
0V
0V
Erase
−10V
Floating
Floating
+6V  
Erase Correction
 +3V
+5V~+6V
0V
0V
Read
+4.5V 
+1V
0V
0V
Bias Voltages for Flash Memory Device Operations
Table 1 shows bias voltages for various operations of a flash memory device. As shown in Table 1, during a programming operation, a source voltage Vs, of the source region
3
, and a bulk voltage Vb of the semiconductor substrate (or bulk region)
2
, are grounded to 0V. A positive high program voltage Vpgm of around 10~20V is applied as a control gate voltage Vg to the control gate
8
, while a drain voltage Vd of approximately 5~6V is applied to the drain region
4
. Using these bias voltages, hot carriers are generated to program the flash memory cell
1
. More specifically, electrons of the bulk region
2
are stored in the floating gate
6
as a result of the electric field generated by the high program voltage Vpgm being applied to the control gate
8
. Meanwhile, charges supplied to the drain region
4
are accumulated, generating the hot carriers. After a flash memory cell
1
has been programmed, it will preferably have a program threshold voltage within a predetermined program voltage distribution area. As shown in
FIG. 2
, a threshold voltage distribution area for an “off” (programmed) cell ranges between approximately 6~8V.
As further shown below in Table 1, during an erasing operation, a negative high erase voltage Vera of approximately −10~−20V is applied as the control gate voltage Vg to the control gate
8
while a voltage of about 5V is applied as the bulk voltage Vb to the bulk region
2
. Using these voltages, a Fowler-Nordheim (F-N) tunneling phenomenon is created to erase the flash memory cell
1
. This F-N tunneling discharges the electrons accumulated in the floating gate
6
, so that the flash memory cells have an erased threshold voltage within a predetermined voltage distribution area. As shown in
FIG. 2
, a threshold voltage distribution area for an “on” (erased) cell ranges from approximately 0.5~2.5V (or between about 1~3V).
In a read operation, a flash memory cell with a high threshold voltage, as a result of the program operation, registers as an “off” cell. This is because current flow from the drain region
4
to the source region
3
is prevented. Because current is permitted to flow from the drain region
4
to the source region
3
during a read operation in a flash memory cell with a low threshold voltage, such a cell appears as an “on” cell.
In a flash memory cell array, the flash memory cells included in one sector are simultaneously erased because they share the same bulk region
2
. Due to the lack of uniformity in threshold voltages between flash memory cells, however, when all of the flash memory cells in a sector are erased at the same time, the threshold voltage of one or more of the flash memory cells often drops below the minimum desirable erased cell threshold voltage distribution level. Erased flash memory cells that have a threshold voltage of 0V or less are called “over-erased memory cells”. To correct over-erased memory cells, a series of over-erase repair operations should be performed. Over-erase repair operations increase the threshold voltage of the over-erased flash memory cells to within the desired erased threshold voltage distribution area.
Referring to
FIG. 3
, a conventional multi-bank NOR flash memory device comprises memory cell arrays
11
,
21
, row decoders
13
,
23
, column decoders
15
,
25
, latch and control circuits
17
,
27
, an input/output (I/O) interface circuit
30
, an erase control circuit
40
, a program control circuit
50
, a block data storage circuit
60
, and a high voltage generation circuit
70
. A nonmulti-bank NOR-type memory device, on the other hand, comprises only a single memory cell array, row decoder, column decoder, and latch and control circuit.
Referring to
FIGS. 1
,
2
, and
3
, in general, operation of the flash memory device is divided into program, erase, and read operations. As mentioned above, the program operation is performed by injecting electrons into the floating gate
6
using hot electrons created at a channel
5
of a memory cell
1
. The erase operation is performed by discharging the electrons in the floating gate
6
to the substrate
2
using F-N tunneling. The read operation is performed by applying a wordline voltage W/L Voltage of around 3.5~5V to a control gate
8
of the memory cell
1
.
It should be noted that the wordline voltage for the read operation is selected between the uppermost erased cell threshold voltage distribution level (approximately 2.5V) and the lowermost programmed cell threshold voltage distribution level (approximately 6V). The multi-bank NOR flash memory device supplies a respectively independent address to the banks
11
,
21
from the I/O interface circuit
30
, thereby enabling an operation such as a read while write (RWW) operation. Those skilled in the art understand the program, erase, and read operations of the multi-bank flash memory device, and a detailed description thereof will therefore be omitted.
The trend in semiconductor memory devices is toward lower operating voltages. A typical flash memory device must operate in an extremely low voltage range (e.g., below 2V or 1.7V). A high voltage generation circuit
70
uses the low operating voltage to generate the high voltages (e.g., the program voltage Vpgm, erase voltage Vera, and read voltage Vrea) supplied to the control gate
8
of the memory cell
1
. This circuit
70
therefore plays an important role in the execution of the cell operations. The design and construction of the high voltage generation circuit
70
is therefore important in maintaining fast operational speeds in the NOR-type flash memory device.
Referring to
FIGS. 3 and 4
, a conventional high voltage generation circuit
70
comprises a program voltage generation circuit
71
, an erase voltage generation circuit
73
, and, a read voltage generation circuit
75
. The program voltage generation circuit
71
generates a program voltage Vpgm by controlling the program control circuit
50
and the latch and control circuits
17
,
27
. The erase voltage generation circuit
73
generates an erase voltage Vera by controlling the erase control circuit
40
and the latch and control circuits
17
,
27
. The read voltage generation circuit
75
generates a read voltage Vrea by controlling the latch and control circuits
17
,
27
. The voltages Vpgm, Vera, and Vrea generated from the voltage generation circuits
71
,
72
,
73
are transferred to the row decoders
13
,
23
through switching means, and are finally transferred to a word line WL selected by the row decoders
13
,
23
. To provide a fast operation speed, the read voltage generation circuit
75
utilizes a boosting circuit.
Referring to
FIG. 5
, the conventional read voltage generation circuit
75
comprises a switch S
1
connected between an input terminal and two capacitors C
1
, CL. A precharge circuit
75
a
is also provided. When the precharge circuit
75
a
precharges a node N
1
up to a power supply voltage VCC level, a boosting operation o

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