Static information storage and retrieval – Read/write circuit – Including reference or bias voltage generator
Reexamination Certificate
1999-09-08
2001-08-21
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Including reference or bias voltage generator
C365S189110, C365S185230
Reexamination Certificate
active
06278639
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a booster circuit having booster cell sections connected in series, which is designed to increase the power voltage, and a voltage generating circuit and a semiconductor memory which use such a booster circuit.
In semiconductor integrated circuits which are equipped with electrically writable/erasable non-volatile memories such as EEPROMs and flash memories, such a high voltage that is required for writing or erasing is generated within a chip by an internal voltage generating circuit, so as to meet the requirement of unifying the power source.
An internal voltage generating circuit consists of a booster circuit for boosting a power voltage supplied from outside, a voltage limiter for adjusting an output voltage of the booster circuit, to a desired voltage value (internal voltage), and a clock generating circuit for controlling the operation of the booster circuit.
FIG. 15
is a circuit diagram equivalent to a conventional internal voltage generating circuit. It should be noted that the circuit shown here is of a type which operates by two-phase clock. In
FIG. 15
, booster cells CP
x
(CP
1
to CP
m
) connected in multiple stages, to each of which a potential is supplied from the power, constitute a booster circuit
10
. Further, a V
XX
limiter circuit
30
is connected to an output node
11
of the booster circuit which outputs an output voltage V
XX
.
The V
XX
limiter circuit
30
monitors the voltage at the output node
11
when an activation signal ACTIVE is at “H” level (/ACTIVE is at “L” level), and further outputs a voltage detection signal V
XX
FLG to a clock generating circuit
20
.
While the activation signal ACTIVE is at “H” level (/ACTIVE is at “L” level) and the voltage detection signal V
XX
FLG is at “L” level, the clock generating circuit
20
outputs a booster clock signal &PHgr;
A
or /&PHgr;
A
by using a clock signal CLK having a predetermined period, and thus the booster circuit
10
carries out a boost operation.
The booster circuit
10
consists of booster cells CP
x
(CP
1
to CP
m
) connected in series in multiple stages, to which clock signal &PHgr;
A
or /&PHgr;
A
is input from the clock generating circuit
20
alternately to every other stage.
For example, the limiter circuit
30
has a structure equivalent to the circuit shown in FIG.
16
. The limiter circuit of
FIG. 16
consists of a resistance element RL connected to the output node
11
shown in
FIG. 15
, an equivalent resistance R1 of a trimming circuit connected to a connection node N
4
which is located on the other side to the output node
1
, a transistor M
3
connected between the equivalent resistance R1 and a ground potential, to a gate of which an activation signal ACTIVE is input, a potential comparator circuit
31
for detecting an output voltage V
XX
by comparing the potential at the connection node N
4
and the reference potential V
ref
, and for detecting a voltage detection signal V
XX
FLG, and a buffer
33
connected to the potential comparator circuit
31
via a connection node
32
, for the voltage detection signal V
XX
FLG.
The limiter circuit
30
is in a non-active state when the activation signal ACTIVE is at “L” level, and the voltage detection signal V
XX
FLG is at “L” level at all times. When the activation signal ACTIVE is at “H” level, the limiter circuit
30
is set in an active state. Further, when the potential at the connection node N
4
is lower than the reference potential V
ref
, the voltage detection signal V
XX
FLG is at “L” level, whereas the potential of the connection node N
4
is higher than the reference potential V
ref
, the voltage detection signal V
XX
FLG is at “H” level. The ratio between RL and R1 is determined so that a voltage V
XX
at the output node
11
becomes to have a desired voltage value, when the connection node N
4
and the reference potential V
ref
are equal to each other.
Let us now consider a case where an output voltage V
XX
of an internal voltage generating circuit containing the booster circuit, is used for writing data in a flash memory or an EEPROM cell. Further, let us take an example of a NAND-type EEPROM in which writing of data is performed by injecting electrons to the floating gate from the channel while applying a high voltage (up to 20V) to the word line (control gate) and applying a substrate potential V
SS
(0V) to a cell. In this case, from the coupling ratio between the voltage applied to the word line and that the voltage applied to the floating gate of the cell, the writing characteristics by the FN tunnel injection are determined. In the NAND-type EEPROM, the writing voltage is, in some cases, stepped up by a voltage of about 0.5V during a writing operation. In this case, such a high accuracy and stability are required in the voltage rise speed that corresponds to the writing time, and the writing voltage for each cell.
FIG. 17
shows a voltage waveform of an output voltage V
XX
in the conventional internal voltage generating circuit shown in FIG.
15
. As the boosting is started from an initial voltage of the booster circuit and the output voltage V
XX
reaches a predetermined voltage, the voltage detection signal V
XX
FLG from the limiter circuit
30
is set to “H” level at a time t
2
, and the clock generating circuit
20
is placed in a non-active state, thus stopping the boosting operation of the booster circuit
10
. The limiter circuit
30
detects an output voltage V
XX
by dividing the resistance, and therefore during the operation (while the activation signal ACTIVE is at “H” level), when a leak current flows from the output node
11
at all times, or there is some other current path which serves as a load connected to the node, the output voltage V
XX
gradually decreases. When the output voltage V
XX
becomes lower than a preset voltage, the voltage detection signal V
XX
FLG is set to “L” level at a time t4. Thus, the clock generating circuit
20
again outputs a clock signal &PHgr;
A
or /&PHgr;
A
, and therefore the booster circuit
10
re-starts the boosting operation. As the booster circuit
10
is set in an active/stop state in accordance with the output from the voltage detection signal V
XX
FLG, the output voltage V
XX
is outputted.
However, the resistance R
L
of the limiter circuit
30
is set in an order of several hundred kilo to M&OHgr; so as to reduce the leak current. Although it depends upon how the resistance element is formed, it is likely to have a very long pattern and a parasitic capacitance is easily created. Such a parasitic capacitance causes a CR delay, and therefore the voltage detection by the limiter circuit
30
is delayed. As a result, the output voltage V
XX
overshoots during a period between t1 and t2, whereas it undershoots during a period between t3 and t4, and thus a potential different of &Dgr;V with respect to the preset voltage is created.
The waveform of such a voltage is determined by the capability of the booster circuit and the size of the leak current of the limiter circuit. The output current of the booster circuit is larger than the leak current of the limiter circuit. Therefore, it is effective to suppress the capability of the booster circuit in order to smallen the potential difference &Dgr;V; however with this method, a rise time up to t1 is delayed. Reversely, if the capability of the booster circuit is enhanced so as to quicken the rise time, the potential difference &Dgr;V further broadens.
In the case where the writing of data is carried out while stepping up the write voltage, it is preferable that each write voltage should be controlled to &Dgr;V which is less than a difference between adjacent step-up voltages. However, due to the above-described reason, it is necessary with the conventional circuit structure that the voltage should be adjusted to an appropriate value where the rise time and voltage difference &Dgr;V are balanced with each other.
As described above, in the conventional booster circuit, the rise characteristics of the boosted potential and the size of the overs
Hosono Koji
Ikehashi Tamio
Imamiya Kenichi
Kanda Kazushige
Nakamura Hiroshi
Hogan & Hartson LLP
Kabushiki Kaisha Toshiba
Le Vu A.
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