Static information storage and retrieval – Read/write circuit – Including level shift or pull-up circuit
Reexamination Certificate
2001-03-21
2002-09-24
Nguyen, Viet Q. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Including level shift or pull-up circuit
C365S189090, C365S226000, C327S535000, C327S536000, C327S541000
Reexamination Certificate
active
06456541
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-080410, filed Mar. 22, 2000, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
This invention relates to a booster circuit having a plurality of booster units (booster cells) whose output terminals are respectively connected to input terminals of the next-stage booster units, for raising voltage by sequentially transferring charges from the input terminals of the booster units to the output terminals thereof in response to clock signals of different phases and more particularly to the technique for resetting the gate nodes of transistors of the booster units in which charges are left behind.
FIG. 1
is a circuit diagram showing an example of the construction of a conventional booster circuit. The booster circuit is described in IEEE Journal of Solid-State Circuits. Vol. 27, No. 11, November 1992, pp. 1540 to 1546, A. Umezawa et al. “A 5-V-Only Operation 0.6-&mgr;m Flash EEPROM with Row Decoder Scheme in Triple Well Structure”.
The booster circuit is constructed by booster units (booster cells)
11
a,
11
b,
booster unit
12
and output circuit section
13
. Each of the booster units
11
a,
11
b,
12
is constructed by two MOS transistors (MOSFETs) and two capacitors and the output terminals thereof are cascade-connected to the input terminals of the next-stage booster units.
That is, the booster unit
11
a
includes N-channel MOS transistors QN
1
, QN
2
and capacitors C
1
, C
2
. One-side ends of the current paths of the MOS transistors QN
1
, QN
2
are connected to a power supply terminal
14
to which a power supply voltage VCC is applied. The other end of the current path of the MOS transistor QN
2
is connected to the gate of the MOS transistor QN
1
and the gate thereof is connected to the other end-of the current path of the MOS transistor QN
1
. One electrode of the capacitor C
1
is connected to the other end of the current path of the MOS transistor QN
1
and the other electrode of the capacitor C
1
is supplied with a clock signal phi
1
. Further, one electrode of the capacitor C
2
is connected to the gate of the MOS transistor QN
1
and the other electrode of the capacitor C
2
is supplied with a clock signal phi
3
.
Likewise, the booster unit
11
b
includes N-channel MOS transistors QN
3
, QN
4
and capacitors C
3
, C
4
. One-side ends of the current paths of the MOS transistors QN
3
, QN
4
are connected to the other end of the current path of the MOS transistor QN
1
. The other end of the current path of the MOS transistor QN
4
is connected to the gate of the MOS transistor QN
3
and the gate thereof is connected to the other end of the current path of the MOS transistor QN
3
. One electrode of the capacitor C
3
is connected to the other end of the current path of the MOS transistor QN
3
and the other electrode of the capacitor C
3
is supplied with a clock signal phi
2
. Further, one electrode of the capacitor C
4
is connected to the gate of the MOS transistor QN
3
and the other electrode of the capacitor C
4
is supplied with a clock signal phi
4
.
The booster unit
12
includes N-channel MOS transistors QN
5
, QN
6
and capacitors C
5
, C
6
. One-side ends of the current paths of the MOS transistors QN
5
, QN
6
are connected to the other end of the current path of the MOS transistor QN
3
. The other end of the current path of the MOS transistor QN
6
is connected to the gate of the MOS transistor QN
5
and the gate thereof is connected to the other end of the current path of the MOS transistor QN
5
. One electrode of the capacitor C
5
is connected to the other end of the current path of the MOS transistor QN
5
and the other electrode of the capacitor C
5
is supplied with the clock signal phi
1
. Further, one electrode of the capacitor C
6
is connected to the gate of the MOS transistor QN
5
and the other electrode of the capacitor C
6
is supplied with a clock signal phi
3
.
The output circuit section
13
is constructed by an N-channel MOS transistor QN
7
. One end of the current path of the MOS transistor QN
7
is connected to the other end of the current path of the MOS transistor QN
3
and the gate thereof is connected to the gate of the MOS transistor QN
5
. Further, a positive voltage VPP obtained by raising or boosting the power supply voltage VCC is output from the other end of the current path of the MOS transistor QN
7
.
With the above construction, when four-phase clock signals phi
1
, phi
2
, phi
3
, phi
4
of different phases are input as shown in the timing chart of
FIG. 2
, the power supply voltage VCC is sequentially raised by the booster circuits
11
a,
11
b
for each cycle of the clock signals and supplied to one end of the current path of the MOS transistor QN
7
. Further, the boosted or raised voltage is supplied to and further raised by the booster unit
12
to produce voltage VG which is in turn supplied to the gate of the MOS transistor QN
7
. Thus, the gate of the transfer MOS transistor QN
7
of the final stage is overdriven by the booster unit
12
so as to prevent a lowering in the output voltage VPP by the threshold voltage of the MOS transistor QN
7
.
In the above four-phase booster circuit, if a high voltage is left behind on the gate node of each MOS transistor in an electrically floating state after termination of the boosting operation, the transfer MOS transistors QN
1
, QN
3
, QN
7
maintain the ON state at the time of re-boosting operation and the boosting operation cannot be effected.
Therefore, as shown in
FIG. 3
, the construction in which resetting N-channel MOS transistors QN
8
to QN
13
are respectively connected between the connection nodes of the gates of the MOS transistors QN
1
to QN
6
and the capacitors C
1
to C
6
and a ground node (GND) is proposed. A reset signal RST is supplied to the gates of the MOS transistors QN
8
to QN
13
.
With the above construction, the gate voltage VG of the transfer MOS transistor QN
7
of the final stage is raised for each cycle of the clock signals phi
1
to phi
4
as shown in the timing chart of FIG.
4
and the output voltage VPP is raised to a desired voltage. Then, if the reset signal RST is set to the high level at the time of termination of the boosting operation to turn ON the MOS transistors QN
8
to QN
13
and ground and discharge the connection nodes of the gates of the MOS transistors QN
1
to QN
6
and the capacitors C
1
to C
6
, then the transfer MOS transistors QN
1
, QN
3
, QN
7
can be forcedly turned OFF, thereby making it possible to prevent occurrence of an erroneous operation in the re-boosting operation.
Further, as shown in
FIG. 5
, the construction in which a resetting N-channel MOS transistor QN
21
is connected between the output node of the power supply voltage VPP and the ground node GND in the booster circuit shown in
FIG. 3
is also known in the art. After termination of the boosting operation, the output node is grounded and reset by supplying the reset signal RST to the gate of the MOS transistor QN
21
.
Thus, in the case of the booster circuit for generating the positive voltage, each node can be relatively easily reset by using the N-channel MOS transistor having a source grounded and a gate supplied with the reset signal having an amplitude between the ground potential and the power supply voltage VCC.
Further, in the above document, a booster circuit for generating a negative voltage as shown in
FIG. 6
is also disclosed. The circuit includes P-channel MOS transistors QP
1
to QP
7
instead of the N-channel MOS transistors QN
1
to QN
7
shown in FIG.
1
. The input terminal of the first-stage booster unit
11
a,
that is, one end of the current path of each of the MOS transistors QP
1
, QP
2
is connected to the ground node GND instead of the power supply terminal
14
.
Likewise, a booster circuit for generating a negative boosted voltage as shown in FIG.
7
and including P-channel MOS transistors QP
1
to QP
13
inste
Banner & Witcoff, LTD.
Kabushiki Kaisha Toshiba
Nguyen Viet Q.
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