Static information storage and retrieval – Read/write circuit – Including reference or bias voltage generator
Reexamination Certificate
2003-01-09
2004-07-13
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Including reference or bias voltage generator
C365S226000, C365S229000
Reexamination Certificate
active
06762960
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a voltage generation circuit for a non-volatile semiconductor memory device. More specifically the invention pertains to a booster circuit that generates a boosted voltage from a power source voltage according to an operation mode.
2. Description of the Related Art
A semiconductor memory device has a memory cell array, in which multiple memory cells are arranged in a matrix. Data reading, programming or writing, and erasing operations with regard to each memory cell are generally carried out by specifying an address in a row direction and a column direction of the memory cell array.
Regulation of a voltage applied to a signal line in the row direction and to a signal line in the column direction connected to each memory cell enables an access to the memory cell, in order to carry out a predetermined operation out of the data reading, programming, and erasing operations. For selection of a certain memory cell, a specific voltage, which is different from a voltage applied to the other memory cells, is generated from a power source voltage and is applied to the certain memory cell.
Recently developed MONOS (Metal Oxide Nitride Oxide Semiconductor or Substrate)-type non-volatile semiconductor memory devices are non-volatile and enable electrical erasing of data. In the MONOS-type non-volatile semiconductor memory device, each memory cell has two memory elements as discussed in a reference Y. Hayashi, et al., 2000 Symposium on VLSI Technology Digest of Technical Papers, pp. 122-123.
As described in this cited reference, in order to gain access to the respective memory elements in such a MONOS-type non-volatile semiconductor memory device, it is required to set, as control voltages, a plurality of different voltages corresponding to the respective signal lines (control lines), which depend upon the number of the memory cells. Different control voltages are also required corresponding to respective operation modes (data reading, data programming, data erasing, and standby modes) with regard to each memory element.
A voltage generation circuit generates such a control voltage. The voltage generation circuit typically includes a booster circuit that boosts the power source voltage according to each of diverse operation modes, and a control voltage generation circuit that receives the boosted voltage and generates a plurality of different control voltages required for the respective operation modes. The booster circuit boosts a power source voltage of, for example, 1.8 V to a high voltage of 8.0 V and outputs the high voltage of 8.0 V as the boosted voltage in the data programming or writing mode and in the data erasing mode, while boosting the power source voltage to a low voltage of 5.0 V and outputs the low voltage of 5.0 V as the boosted voltage in the data reading mode and in the standby mode. The MONOS memory cell requires a higher voltage than the power source voltage in the data reading mode. Generation of a higher voltage than the power source voltage is also required in the standby mode, in order to shorten an access time in which the operation mode is changed over from the standby mode to the data reading mode. The boosted voltage of 5.0 V in the standby mode may hereafter be referred to as the standby voltage.
An access to the memory element is required in the active modes, for example, in the data reading mode, in the data programming mode, and in the data erasing mode, among the operation modes. The memory cell array accordingly requires a large electric power. In the standby mode, on the other hand, no access to the memory element is required. It is accordingly desirable to reduce the current consumption in the standby mode.
A proposed booster circuit has a first booster module having a large current capacity supplied to a loading (for example, a memory cell array) and a second booster module having a smaller current capacity and thereby a less current consumption than those of the first booster module. In the active mode, the first booster module having the large current capacity is used to boost the power source voltage and ensure a sufficient supply of electric power required for the memory cell array. In the standby mode, on the other hand, while the first booster module is at a stop, the second booster module having the smaller current capacity and thereby the less current consumption is driven and used to boost the power source voltage. This arrangement reduces the current consumption by the booster circuit in the standby mode.
The proposed booster circuit, however, has some problems discussed below at the power supply ON time or at the reset time of the non-volatile semiconductor memory device.
Immediately after the power supply ON time or the reset time of the non-volatile semiconductor memory device, the memory device is in the standby mode. In the booster circuit, the second booster module is accordingly driven, while the first booster module is kept at a stop. At the power supply ON time or at the reset time, however, the boosted voltage output from the booster circuit is initially close to the power source voltage. It is required to quickly raise the boosted voltage from the power source voltage level to the standby voltage level (for example, 5.0 V). The second booster module has the smaller current capacity and thus requires an undesirably long time to raise the boosted voltage from the power source voltage to the standby voltage. This results in extending the time period between the power supply ON time or the reset time and the time to permit an access to the memory element (initial access permission time).
SUMMARY OF THE INVENTION
The advantage of the present invention is thus to solve the problems of the prior art technique discussed above and to provide a booster circuit for a non-volatile semiconductor memory device, which shortens an initial access permission time at a power supply ON time or at a reset time.
In order to attain at least part of the above and the other objects, the present invention is directed to a booster circuit applied for a non-volatile semiconductor memory device, which includes a memory cell array of multiple non-volatile memory elements and has multiple operation modes including a plurality of active modes to permit an access to one of the multiple non-volatile memory elements and a standby mode to stand ready for an access to one of the multiple non-volatile memory elements. The booster circuit boosts a power source voltage and outputs a boosted voltage according to each of the operation modes. The booster circuit includes: a first booster module that is driven in each of the active modes to boost the power source voltage to a specified voltage according to the active mode and output the specified voltage as the boosted voltage; a second booster module that has a smaller current capacity supplied to the memory cell array than that of the first booster module, and is driven in the standby mode to boost the power source voltage to a standby voltage according to the standby mode and outputs the standby voltage as the boosted voltage; and a drive control module that controls actuation of the first booster module and the second booster module. At a power supply ON time or at a reset time of the non-volatile semiconductor memory device, the drive control module actuates the first booster module to make the boosted voltage rise to the standby voltage even when the operation mode is the standby mode.
At the power supply ON time or at the reset time, the first booster module is driven and used to boost the power source voltage. The first booster module has the greater current capacity and thereby enables the boosted voltage to be quickly raised from the power source voltage to the standby voltage, compared with the second booster module. This arrangement significantly shortens the time period required for boosting the voltage to the standby voltage level, thus remarkably reducing the time period between the power supply ON time or the reset time and
Le Vu A.
Oliff & Berridge, plc
Seiko Epson Corporation
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