Static information storage and retrieval – Read/write circuit – Including reference or bias voltage generator
Reexamination Certificate
2002-02-27
2003-08-19
Ho, Hoai (Department: 2818)
Static information storage and retrieval
Read/write circuit
Including reference or bias voltage generator
C365S185230, C365S226000, C327S536000
Reexamination Certificate
active
06608782
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a booster circuit for a nonvolatile semiconductor memory device, in particular, a booster circuit having a capacitor made of a dielectric film.
Conventionally, the most widely used flash memories (batch erase type memory) include ETOX (EPROM Thin Oxide: a registered trademark of Intel).
FIG. 11
shows a schematic cross sectional view of this ETOX-type flash memory cell. As shown in
FIG. 11
, a floating gate
5
is formed on a source
1
, a drain
2
and a substrate (well)
3
between the source and the drain via a tunnel oxide film
4
. Furthermore, a control gate
7
is formed on the floating gate
5
via an interlayer insulating film
6
.
The operation principles of the ETOX-type flash memory are explained below. As shown in Table 1, a voltage Vpp (for example, 9 V) is applied to the control gate
7
, a standard voltage Vss (for example, 0 V) is applied to the source
1
and a voltage of 6 V is applied to the drain
2
during a write operation. Consequently, a large amount of currents flow into a channel layer, channel hot electrons are generated in a portion on the drain
2
side having a high electric field and electrons are injected into the floating gate
5
. As a result, the threshold voltage of a memory cell
8
is increased and data is written to the memory cell
8
.
FIG. 12
shows a threshold voltage distribution in a written state and an erased state. As shown in
FIG. 12
, the threshold voltage of the written memory cell is 5 V or higher.
TABLE 1
Control
gate 7
Drain 2
Source 1
Substrate 3
Write
9 V
6 V/0 V
0 V
0 V
Erase
−7.5 V
Open
4 V
0 V
Read
5 V
1 V
0 V
0 V
Furthermore, during an erase operation, a voltage Vnn (for example, −7.5 V) is applied to the control gate
7
and a voltage Vpe (for example, 4 V) is applied to the source
1
. Consequently, the drain
2
is opened, and a strong electric field is generated in the tunnel oxide film
4
between the source
1
and the floating gate
5
. Then, electrons are pulled from the floating gate
5
to the source
1
side by Fowler-Nordheim (FN) tunneling to decrease the threshold voltage of the memory cell
8
. As a result, the threshold voltage of the erased memory cell
8
becomes 1.5 to 3 V as shown in FIG.
12
.
Furthermore, during a read operation, a voltage of 1 V is applied to the drain
2
and a voltage of 5 V is applied to the control gate
7
. Here, when the memory cell
8
is in an erased state and has a low threshold voltage, currents flow into the memory cell
8
and a state “1” is determined. On the other hand, when the memory cell
8
is in a written state and has a high threshold voltage, currents do not flow into the memory cell and a state “0” is determined.
Meanwhile, when a nonvolatile semiconductor memory device using the ETOX-type flash memory cell or the like is driven, for example, in a case where an external power source voltage Vcc is 5 V, voltages other than the externally supplied power source voltage Vcc (5 V) (in the above example, voltages Vpp, Vnn and the like) are required in a drive system of the nonvolatile semiconductor memory device.
FIG. 13
shows a block diagram of a voltage generation system in this case.
As shown in
FIG. 13
, three booster circuits (voltage pumps) are provided in the voltage generation system of the nonvolatile semiconductor memory device. One is a first high voltage pump
14
. This first high voltage pump
14
generates a bit line voltage and transmits it to a Y decoder
12
during a write operation to respective memory cells
8
constituting a memory cell array
11
. Meanwhile, during an erase operation, the pump generates a source voltage and transmits it to a source switch circuit
13
to apply the voltage to the source
1
of the memory cell
8
. It is noted that an output voltage of the first high voltage pump
14
is lowered to 4 V during the erase operation. Another pump is a second high voltage pump
16
, which generates a word line voltage during a write operation and transmits it to an X decoder
15
. The other pump is a negative voltage pump
17
, which generates a negative voltage for a word line (control gate
7
) during an erase operation and transmits it to the X decoder
15
.
The outputs of the first high voltage pump
14
and the second high voltage pump
16
are used as power sources for a level shifter circuit or the like in the Y decoder
12
and the source switch circuit
13
. Table 2 shows values of maximum voltages outputted from the voltage pumps
14
,
16
,
17
.
TABLE 2
Voltage
First high voltage pump 14
6 V
Second high voltage pump 16
9 V
Negative voltage pump 17
−7.5 V
FIG. 14
shows an example of these voltage pumps generating voltages.
FIG. 14
is a circuit diagram of the second high voltage pump
16
, which is constituted by a plurality of n-MOS (metal oxide film semiconductor) transistors and a plurality of capacitors. An external power source voltage Vcc is boosted by inputting a clock CLK to output a higher voltage.
FIG. 15
shows changes in the voltage of each node with time in this case (for example, in the case of Vcc=5 V). The voltage of each node in
FIG. 15
is an average voltage value. Although it is not shown, the voltage is actually amplified in synchronization with the clock CLK. As shown in
FIG. 15
, the voltage of each node is gradually increased with time and reaches a prescribed voltage for each node. It is noted that the output voltage of the second high voltage pump
16
in this case is 9 V (not shown).
FIG. 16
shows details of a voltage waveform immediately after the voltage of node
4
is increased and reaches the prescribed voltage 11.2 V, that is, a voltage waveform at the encircled point in FIG.
15
. As shown in
FIG. 16
, when the clock CLK
2
of Vss is inputted into the capacitor C
4
((0 V)→Vcc (5 V)), the voltage of the node
4
is increased from 7 V to 11.2 V. As a result, a voltage of 9 V on average can be obtained at the output stage. This output voltage of 9 V finally becomes a word line voltage during a write operation.
FIG. 17
shows a circuit of the negative voltage pump
17
. It has a basic constitution that is similar to that of the second high voltage pump
16
and is constituted by a plurality of p-MOS transistors and a plurality of capacitors. Furthermore, an external voltage Vss is lowered by inputting a clock CLK to output a negative voltage.
FIG. 18
shows changes of the voltage of each node with time in this case. The voltage of each node changes with time and reaches a prescribed voltage for each node.
FIG. 19
shows details of a voltage waveform at the encircled point in FIG.
18
. As shown in
FIG. 19
, when the clock CLK
2
(Vcc (5 V)→Vss (0 V)) is inputted into the capacitor C
4
, the voltage of the node
4
is lowered from −5.8 V to −9.8 V. As a result, a voltage of about −7.5 V on average can be obtained at the output stage. This output voltage of −7.5 V finally becomes a gate line voltage during an erase operation.
However, the above conventional booster circuit of a nonvolatile semiconductor memory device has the following problems. That is, in the case of the second high voltage pump
16
having a configuration shown in
FIG. 14
, the voltage of the node
4
is 7 V when the clock CLK
2
is 0 V, while it is 11.2 V when the clock CLK
2
is 5 V. Therefore, the voltage applied to the capacitor C
4
becomes 7 V when the clock CLK
2
is 0 V, while it is 6.2 V when the clock CLK
2
is 5 V. Here, when the withstand voltage of an insulating film constituting a dielectric film of the capacitor C
4
is 6.5 V, a voltage applied when the clock CLK
2
is 0 V, which is 7 V, exceeds the withstand voltage. Therefore, the insulating film may be damaged in the worst case.
As one of methods for solving this problem, in a semiconductor integrated circuit disclosed in Japanese Patent Laid-Open Publication No. 5-28786, a thick oxide film is used as a d
Auduong Gene N.
Morrison & Foerster / LLP
Sharp Kabushiki Kaisha
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