Booster circuit and semiconductor memory device having the same

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36518911, 327536, 327537, G11C 700

Patent

active

060410116

ABSTRACT:
In a booster circuit, a gate of an input-side transistor whose end is supplied with a power supply voltage is supplied with an inverted signal of a signal supplied to a signal input terminal of a booster unit at a first stage or supplied with an AND signal of the inverted signal and a booster circuit activation signal. Therefore, when the transistor at the first stage operates, the input-side transistor is turned off. Accordingly, a back flow of a current from inside the booster circuit to a power supply is prevented, so that the efficiency of the booster circuit can be improved. Further, fluctuations of the output voltage are not brought about even when the power supply voltage greatly fluctuates, so that the reliability of peripheral elements and memory cells can be improved and the allowable range of an external power supply voltage can be widened.

REFERENCES:
patent: 4837466 (1989-06-01), Kanauchi
patent: 5499209 (1996-03-01), Oowaki et al.
patent: 5589793 (1996-12-01), Kassapian
patent: 5642072 (1997-06-01), Miyamoto et al.
patent: 5644534 (1997-07-01), Soejima
patent: 5650741 (1997-07-01), Nakamura et al.
patent: 5812018 (1998-09-01), Sudo et al.
patent: 5815446 (1998-09-01), Tobita
patent: 5841703 (1998-11-01), Wojciechowski

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