Boosted voltage generating circuit and semiconductor memory...

Details Boosted voltage generating circuit and semiconductor memory... Boosted voltage generating circuit and semiconductor memory...

2001-05-25

2002-11-26

Phan, Trong (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185270, C365S185330

Reexamination Certificate

active

06487120

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-154983, filed May 25, 2000, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
This invention relates to a boosted voltage generating circuit for boosting power supply voltage and a semiconductor memory device having the same and more particularly to a semiconductor memory device having memory cells and a boosted voltage generating circuit for generating high voltage used at the data erasing or programming time of the memory cell.
A flash memory is provided as one type of a semiconductor memory device.
FIG. 1
shows the cross sectional construction of one memory cell element of the flash memory. In
FIG. 1
, an N-type well region (N-well)
72
is formed in a P-type semiconductor substrate (P-substrate)
71
. Further, a P-type well region (P-well)
73
is formed in the N-type well region
72
. In the P-type well region
73
, source and drain regions
74
,
75
of a memory cell which are formed of n
+
-type regions are separately formed. A floating gate electrode
76
is formed above the channel region between the source and drain regions
74
and
75
with an insulating film disposed therebetween and a control gate electrode
77
is formed above the floating gate electrode
76
with an insulating film disposed therebetween.
Further, a contact region
78
formed of a p
+
-type region is formed on the P-substrate
71
, a contact region
79
formed of an n
+
-type region is formed on the N-type well region
72
and a contact region
80
formed of a p
+
-type region is formed on the P-type well region
73
.
At the operating time, gate voltage Vg, drain voltage Vd and source voltage Vs are respectively applied to the control gate electrode
77
, drain region
75
and source region
74
. Further, the same voltage as the source voltage Vs is applied to the contact regions
79
and
80
and a ground voltage of 0V is applied to the contact region
78
.
The above memory cell stores data of “1” or “0” level according to the amount of electrons accumulated in the floating gate electrode
76
. The threshold voltage as viewed from the control gate electrode
77
is changed according to the level of the stored data.
A memory cell array is constructed by use of a plurality of memory cells which have the same construction as the above memory cell.
FIG. 2
shows an example of a circuit of the memory cell array of a NOR type flash memory. A plurality of memory cells MC are arranged in a matrix form and the control gate electrodes of the memory cells MC arranged on the same row are commonly connected to a corresponding one of a plurality of word lines WL
0
to WLn. Further, the drains of the memory cells MC arranged on the same column are commonly connected to a corresponding one of a plurality of bit lines BL
0
to BLm. Generally, the memory cells are divided into a plurality of blocks and the sources of the memory cells MC in the same block are commonly connected to a corresponding one of a plurality of source lines SLi which is provided for the block.
FIG. 3
shows the relation between the gate voltage (Vg) applied to the control gate electrode and a drain current flowing in the memory cell at the operating time. In this example, the state in which the amount of electrons accumulated in the floating gate electrode is relatively large, that is, the state in which the threshold voltage Vt of the memory cell is high is defined as “0” data (the memory cell storing “0” data is referred to as a “0” cell) and the state in which the amount of accumulated electrons is relatively small, that is, the state in which the threshold voltage Vt of the memory cell is low is defined as “1” data (the memory cell storing “1” data is referred to as a “1” cell).
One example of the voltage bias condition at the data readout time, program time and erase time is shown in the following table 1.
TABLE 1
Readout
Program
Erase
Vg
5 V
9 V
−7 V
Vd
1 V
5 V(“1”)
Floating
0 V(“0”)
Vs
0 V
0 V
10 V
That is, the table 1 shows one example of values of the voltages Vg, Vd, Vs supplied to the memory cell. At the data readout time, Vg, Vd, Vs are respectively set at 5V, 1V, 0V. At the data program time, Vg, Vs are respectively set at 9V, 0V and Vd is set at 5V for the memory cell into which data is programmed and at 0V for the other memory cells (in which original “1” data is kept). Further, at the data erase time, Vg, Vs are respectively set at −7V, 10V and Vd is set in the electrically floating state.
Readout data is determined according to whether a cell current flows or not when voltage Vread (in this example, 5V) is applied to the control gate electrode while preset voltage (in this example, 1V) is being applied to the drain. The above determination is made by comparing the cell current with a reference current (Iref) flowing in a reference cell by use of a sense amplifier (not shown).
The erase operation is simultaneously effected for a plurality of memory cells which commonly have the P-well
73
(shown in FIG.
1
). At the erase time, all of the memory cells subjected to the erase process are set into “1” cells by causing electrons to flow from the floating gate electrodes
76
thereof into the P-type well region
73
according to the Fowler-Nordheim (F•N) tunneling phenomenon.
The program operation is effected for each memory cell. The bit line connected to the memory cell in which “0” data is programmed is biased to 5V so as to inject electrons of high energy generated by the channel hot electron phenomenon into the floating gate electrode
76
of the memory cell. The bit line connected to the “1” cells in which original “1” data is maintained is set at 0V. As a result, no electrons are injected into the floating gate electrode
76
and the threshold voltage Vt is kept unchanged in the non-programmed memory cell.
Further, in the flash memory, the program verify operation and erase verify operation are effected at the program time and erase time to confirm the extent to which data is programmed and erased. In the program verify operation, the “0” readout operation is effected by setting the voltage of the control gate electrode at high voltage Vpv (for example, 7V) in comparison with the voltage Vread (in this example, 5V) set at the readout time. Then, the program operations and program verify operations are repeatedly and alternately effected and the program operation is terminated when data items of the memory cells to be programmed are all set to “0”.
At the erase time, the “1” readout operation is effected by setting the voltage of the control gate electrode
77
at low voltage Vev (for example, 3.5V) in comparison with the voltage Vread set at the readout time. Then, the erase operations and erase verify operations are repeatedly and alternately effected and the erase operation is terminated when data items of the memory cells subjected to the erase process are all set to “1”. As a result, a sufficiently large cell current Icell can be attained.
Thus, the voltage applied to the control gate electrode of the memory cell is set to various values such as 9V, 7V, 5V, 3.5v according to the various operation modes. Among the above voltages, 9V, 7V, 5V are higher than the power supply voltage supplied from the exterior.
Conventionally, in order to generate various voltages such as 9V, 7V, 5V which are higher than the power supply voltage supplied from the exterior, a required number of booster circuits for boosting the power supply voltage are provided and one of the outputs of the plurality of booster circuits is adequately selected by use of a switch and the selected output is applied to the control gate electrode of the memory cell.
However, since the booster circuit necessitates elements such as capacitors which occupy a large area on the chip, there occurs a problem that the chip area becomes large if a plurality of booster circuits are provided. Further, since the consumption current

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