Static information storage and retrieval – Read/write circuit – Including level shift or pull-up circuit
Reexamination Certificate
2000-12-18
2001-12-04
Nguyen, Viet Q. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Including level shift or pull-up circuit
C365S226000, C365S230060
Reexamination Certificate
active
06327195
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to boosted-voltage drive circuits which drive a voltage boosted as compared to an external power supply voltage, and semiconductor devices employing the same.
2. Description of the Background Art
In semiconductor integrated circuit devices, e.g. semiconductor memory devices, a power supply voltage lower than an external power supply voltage Vdd can be generated on chip and supplied as an internal power supply voltage Vcc to ensure reliability and the like. In semiconductor devices, dynamic random access memories (DRAMs) in particular, however, a voltage boosted as compared to an external power supply potential can be generated on chip as a potential to drive a word line for selecting a memory cell.
FIG. 28
is a schematic block diagram showing a configuration of a memory array in a conventional DRAM.
A memory array MA is divided into blocks or a plurality of memory sub arrays SMA
1
to SMAn. Sense amplifier bands SAB
1
to SABn−1 have any sense amplifier band SABj shared e.g. by adjacent memory sub arrays SMAj and SMAj+1. Furthermore, sense amplifier bands SAB
0
and SABn are provided outside memory sub arrays SMA
1
and SMAn, respectively.
Memory sub arrays SMA
1
to SMAn are provided with block row decoders BRD
1
to BRDn, respectively. Sense amplifier bands SAB
1
to SABn−1 are provided with sense amplifier control circuits SAC
0
to SACn, respectively.
There are also provided word line drivers WD
1
to WDn which respond to a signal decoded by block row decoders BRD
1
to BRDn to drive the potential level of the corresponding word line to an active level (potential Vpp).
For example, when memory sub array SMA
1
is selected in response to an externally applied row address signal, word line driver WD
1
powered with a boosted voltage starts to operate according to a result obtained from the address signal decoded by block row decoder BRD
1
and drives a selected word line in memory sub array SMA
1
to the potential Vpp level.
The data read from a memory cell thus selected is amplified by a sense amplifier of sense amplifier band SAB
1
via a bit line. When the read cycle completes, word line driver WD
1
again operates to decrease the potential level of the word line from the potential Vpp level to a ground potential level (GND level).
In addition, for example, a bit-line isolation signal line is provided to control a block select transistor for providing isolation of a bit line between memory sub array SAB
1
and sense amplifier band SAB
1
. As is similar to a word line, the bit-line isolation signal line transmits a signal which is driven to attain potential level Vpp.
In a standby state the bit-line isolation signal line is held at potential level Vpp so as to prevent drop of the voltage corresponding to the threshold voltage of the block select transistor. When a read cycle is started, before the potential level of a word line initially rises to a selected, potential level (Vpp) the bit-line isolation signal line for selectively providing isolation of a bit line between non-selected memory sub array SMA
1
and sense amplifier band SAB
1
falls from potential level Vpp to the GND level. When the read cycle completes, the bit-line isolation signal line for the non-selected memory sub array SMA
1
again rises to potential level Vpp.
FIG. 29
is a circuit diagram for illustrating a configuration of sense amplifier band SABi shown in FIG.
28
.
Sense amplifier band SAB
1
includes a sense amplifier SA including an n-channel transistor amplifier configured of n-channel MOS transistors N
10
and N
12
and p-channel transistor amplifier configured of p-channel MOS transistors P
10
and P
12
, and block select gate BSG
1
responsive to a signal ISO
1
for selectively opening and closing a connection between sense amplifier SA and a pair of bit lines BL
1
,/BL
1
in memory sub array SMA
1
.
BSG
1
includes an n-channel MOS transistor N
20
having its gate potential driven by a bit-line isolation signal line ISO
1
for opening and closing a connection of bit line BL
1
to one input node of sense amplifier SA, and n-channel MOS transistor N
22
having its gate potential driven by signal ISO
1
transmitted on bit-line isolation signal line ISO
1
for selectively opening and closing a connection of bit line /BL
1
to the other input node of sense amplifier SA.
Sense amplifier band SAB
1
also includes a block select gate BSG
2
which selectively opens and closes a connection between a pair of bit lines BL
2
, /BL
2
in memory sub array SMA
2
and sense amplifier SA. Block select gate BSG
2
includes an n-channel MOS transistor N
24
having its gate potential driven by a bit-line isolation signal line ISO
2
for selectively opening and closing a connection between bit line BL
2
and one input node of sense amplifier SA, and an n-channel MOS transistor N
26
having its gate potential driven by signal line ISO
2
for selectively opening and closing a connection between bit line /BL
2
and the other input node of sense amplifier SA.
Sense amplifier band SAB
1
also includes a select gate SG opening and closing a connection between an associated I/O line pair and an associated bit line pair in response to a column select signal YL from a column decoder CLD, and a precharge circuit PCC responsive to a precharge signal RP for precharging an associated bit line pair to attain a precharge potential Vcc/2 corresponding to half the potential level of internal power supply potential Vcc.
As described above, bit-line isolation signal lines ISO
1
and ISO
2
are also driven to the level of boosted potential Vpp.
FIG. 30
is a circuit diagram illustrating a configuration of a first conventional level shifter circuit
9000
for converting a signal having the logical amplitude of the internal power supply potential Vcc level to that having the logical amplitude of the boosted voltage Vpp level in a circuit block powered with boosted voltage Vpp as described above.
Level shifter circuit
9000
includes p-channel MOS transistors P
30
and P
32
having their respective sources receiving power supply potential Vpp and their respective gates and drains cross-coupled with each other, and n-channel MOS transistors N
30
and N
32
respectively connected between the drains of p-channel MOS transistors P
30
and P
32
and ground potential GND.
The gate of n-channel MOS transistor N
30
is driven by an input signal IN having the logical amplitude of internal power supply voltage Vcc. The gate of n-channel MOS transistor N
32
is driven by a signal output from an inverter INV
1
driven by power supply potential Vcc and receiving and inverting signal IN for output.
FIG. 31
is a timing chart for representing an operation of level shifter circuit
9000
shown in FIG.
30
.
At time t1, input signal IN rises from ground potential GND to internal power supply potential Vcc and responsively transistor N
30
is turned on and the gate potential of p-channel MOS transistor P
32
rises to ground potential GND. Responsively transistor P
32
is turned on, while the output from inverter INV
1
attains the GND level and responsively a signal OUT rises to boosted potential Vpp at time t2, since n-channel MOS transistor N
32
has been turned off.
At time t3, input signal IN falls to ground potential GND and responsively transistor N
30
is turned off and transistor N
32
is turned on. Since transistor P
30
turned off allows the gate of transistor P
32
to be charged to attains potential level Vpp, transistor P
32
is turned off and transistor N
32
turned on thus allows output signal OUT to fall to ground potential GND at time t4.
FIG. 32
is a circuit diagram for illustrating a configuration of a second conventional level shifter circuit
9200
.
Level shifter circuit
9200
differs in configuration from level shifter circuit
9000
, as described below.
That is, transistor N
30
is replaced by a transistor N
40
receiving power supply potential Vcc at its gate and input signal IN at its source, and transistor N
32
is replaced
Ooishi Tsukasa
Shimano Hiroki
Tomishima Shigeki
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Nguyen Viet Q.
LandOfFree
Boosted-voltage drive circuit operable with high reliability... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Boosted-voltage drive circuit operable with high reliability..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Boosted-voltage drive circuit operable with high reliability... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2591452