Boosted potential generation circuit and control method

Static information storage and retrieval – Read/write circuit – Including level shift or pull-up circuit

Reexamination Certificate

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C365S149000, C327S536000

Reexamination Certificate

active

06954386

ABSTRACT:
A boosted potential generation circuit enables a high-speed operation and even miniaturization in a semiconductor memory even if external power supply voltage is reduced in the semiconductor memory. In the boosted potential generation circuit provided with a capacitor MOS transistor and a transfer MOS transistor and used for a DRAM including memory cells, a gate insulating film of the capacitor MOS transistor is thinner than that of the MOS transistor constituting the memory cell to realize a boosted potential generation circuit which has a small area and a large capacity. In this case, preferably, the gate insulating film of the transfer MOS transistor has a thickness which is not greater than that of the gate insulating film of the capacitor MOS transistor.

REFERENCES:
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patent: 6166585 (2000-12-01), Bazzani
patent: 6195305 (2001-02-01), Fujisawa et al.
patent: 6288601 (2001-09-01), Tomishima
patent: 6316985 (2001-11-01), Kobayashi et al.
patent: 6522191 (2003-02-01), Cha et al.
patent: 6-283667 (1994-10-01), None
patent: 11110992 (1999-04-01), None
patent: 11-297950 (1999-10-01), None
patent: 2000-112547 (2000-04-01), None
Taiwanese Office Action date Aug. 30, 2004 with Translation.
Korean Office Action dated Apr. 29, 2005 with partial translation.

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