Boosted multiplexer transmission gate

Details Boosted multiplexer transmission gate Boosted multiplexer transmission gate

2000-12-29

2002-06-11

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Field-effect transistor

C326S088000, C326S106000, C327S390000, C327S408000

Reexamination Certificate

active

06404237

ABSTRACT:

FIELD OF THE INVENTION
The present invention is related to an apparatus and method for boosting transmission gates to speed the transmission of digital signals by transmission gates in multiplexed circuits.
BACKGROUND OF THE INVENTION
Commonly available electronic devices use transmission gates to output digital signals to other devices. It is often necessary to output a single digital signal to a node to which many devices are attached, especially in the case of multiplexers, where the outputs of many devices such as transmission gates are attached to a single node. Having so many devices attached to a single node increases the capacitive load, which in turn, increases the time required by a transmission gate to raise or lower the voltage of a node to the level at which the node is to be driven.
Prior solutions to overcome this capacitive load often entail using more powerful transmission gates, and this is often done by designing transmission gates that are physically larger. However, such prior designs for increasing the power of transmission gates have suffered the drawbacks of increased power consumption, increased delays in response time by the transmission gate, and actually further increasing the capacitive load that is sought to be overcome. Indeed, the increase in capacitive load caused by the use of more powerful transmission gates can actually defeat the benefits sought to the extent that the result of using a more powerful transmission gate is actually worse, especially where the outputs of multiple ones of such powerful transmission gates are attached to the same node, as would often occur in multiplexers. Furthermore, these drawbacks of increased power consumption and increased response time have become of ever increasing concern as desires for ever greater power conservation and circuit speed have continued to grow.
FIG. 1
is a schematic diagram of a prior art transmission gate. Circuit
100
is comprised of enable input
110
, inverter
112
, data input
120
, data output
122
, NMOS transistor
130
, and PMOS transistor
140
. Circuit
100
is designed to allow signals to pass through from data input
120
to data output
122
in response to enable input
110
being driven low, i.e., to 0. PMOS transistor
140
receives enable input
110
, directly, and allows signals to pass from data input
120
to data output
122
in response to enable input
110
being driven low, i.e., being driven to closer to 0 volts than to VCC. Correspondingly, NMOS transistor
130
receives an inverted form of enable input
110
, indirectly, through inverter
112
, and allows signals to pass from data input
120
to data output
122
also in response to enable input
110
being driven low. Delays are incurred arising from the time required for transistors
130
and
140
to respond to changes between high and low of enable input
110
, and further delays are incurred if circuit
100
is used to pass a signal from data input
120
to a data output
122
that is connected to many other devices, as would commonly occur where circuit
100
is part of a multiplexer, or to a data output
122
that is connected to a lengthy transmission line.


REFERENCES:
patent: 6072354 (2000-06-01), Tachibana et al.

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