Boosted drive system for master/local word line memory architect

Details Boosted drive system for master/local word line memory architect Boosted drive system for master/local word line memory architect

1991-12-18

1993-10-19

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Including reference or bias voltage generator

36518911, 365226, G11C 700

Patent

active

052552241

ABSTRACT:
An integrated boost and local word line drive system that enhances the speed of the word line drive without providing excessive voltage stresses to the driver devices. A charge reservoir stores a boost voltage under the control of a charge pump that is regulated by a voltage regulator. One of the local word lines coupled to a selected master word line is enabled by a driver that receives the boost voltage. The switching times and signal slew rates of the driver, as well as the boost voltage, are controlled to prevent excessive gate stresses in the support circuitry.

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R. Scheuerlein et al., "Offset Word Line Architecture for Scaling DRAMs to the Gigabit Level," Center for Integrated Systems, 1987 Symposium on VLSI Circuits, Session VI-4, pp. 81-82.

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