Miscellaneous active electrical nonlinear devices – circuits – and – Gating – Signal transmission integrity or spurious noise override
Reexamination Certificate
2002-06-06
2004-02-17
Nuton, My-Trang (Department: 2819)
Miscellaneous active electrical nonlinear devices, circuits, and
Gating
Signal transmission integrity or spurious noise override
C327S536000
Reexamination Certificate
active
06693479
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to switched-capacitor systems and, more particularly, to boost structures in these systems.
2. Description of the Related Art
FIG. 1
illustrates a switched-capacitor system
20
in which a sample capacitor C
s
has a top plate
21
coupled to the inverting input of a differential amplifier
22
and a bottom plate
23
coupled through an input sample switch
24
to an input port
25
. The differential amplifier
22
drives an output port
26
and a transfer capacitor C
t
is coupled across the differential amplifier. The differential amplifier has a high gain so that its non-inverting input has substantially the same potential as its inverting input. Finally, a second sample switch
27
and a transfer switch
28
are respectively coupled to the top and bottom plates
21
and
23
.
In an operational sample mode, the input and second sample switches
24
and
27
are closed (as shown in
FIG. 1
) so that an analog input signal S
in
at the input port
25
urges an electrical sample charge Q
s
into the sample capacitor C
s
to thereby generate a sample signal S
s
=Q
s
/C
s
across the sample capacitor.
In an operational transfer mode, the first and second sample switches
24
and
27
are opened and the transfer switch
28
is closed. The bottom plate
23
is thus grounded through the closed, transfer switch. Because the signal across the sample capacitor C
s
is now substantially zero, the sample charge Q
s
is transferred into the transfer capacitor C
t
to generate an output processed signal S
prcsd
=Q
s
/C
t
at the output port
26
. The sample and transfer operations of
FIG. 1
thereby generate a S
prcsd
/S
in
transfer function of C
s
/C
t
and this transfer function is represented in the graph
30
of
FIG. 2
by a plot
32
which has a slope of C
s
/C
t
.
The switched-capacitor system
20
(and differential versions thereof) is especially suited for use as a sampler in a variety of signal conditioning systems (e.g., a pipelined analog-to-digital converter (ADC)). In such systems, the switches of the system
20
of
FIG. 1
are typically realized with complementary metal-oxide-semiconductor (CMOS) transistors. This realization is exemplified in
FIG. 1
by a CMOS transistor
34
that is substituted for the input sample switch as indicated by the substitution arrow
35
.
In pipelined ADCs, an initial ADC stage (e.g., a flash ADC) typically converts an analog input signal into at least one most-significant bit D
o
of a digital output signal that corresponds to the input signal S
in
. At the same time, the sampled signal is processed into a residue signal S
res
that is suitable for subsequent processing by downstream ADC stages into the less-significant bits of the output digital signal.
If the initial ADC stage is a 1.5 bit converter stage, for example, it provides a residue signal S
res
that corresponds to the plot
36
in
FIG. 2
which has two steps
37
that are equally spaced from the midpoint of the range of the input signal S
in
. The steps are initiated by decision signals from the initial ADC stage. The plot
36
of the residue signal S
res
has three segments defined by the steps
37
and each segment has a slope that is twice the slope of the plot
32
.
The residue signal illustrated by the plot
36
can be generated, for example, by supplementing the sample capacitor C
s
of
FIG. 1
with an additional sample capacitor to realize the increased slope (i.e., increased gain) and by replacing the transfer switch
28
with a multipole transfer switch
38
as indicated by the substitution arrow
39
. The transfer switch responds to digital decision signals S
dgtl
from the initial ADC stage by applying selected offset signals (e.g., +V and −V) to the bottom plates of the sample capacitors. The offset signals generate the steps
37
in the plot
32
of FIG.
2
. When the switched-capacitor system
20
of
FIG. 1
is modified in this fashion, it is typically referred to as a multiplying digital-to-analog converter (MDAC).
Accuracy and bandwidth of switched-capacitor structures is strongly dependent upon the on resistance r
on
of its switches. For example, the on resistance r
on
of the input sample switch
24
of FIG.
1
and the capacitance of the sample capacitor establishes (along with the on resistance r
on
of the second sample switch
27
) a time constant for acquisition of the analog input signal S
in
. The switch on resistance r
on
thus limits the acquisition time and the bandwidth of switched-capacitor structures. More importantly, the on resistance r
on
of the input sample switch
24
will vary with the input signal S
in
thus inducing distortion in the sampled charge Q
s
.
Although the on resistance r
on
can be reduced by using a larger device (i.e., a larger CMOS transistor
34
in FIG.
1
), this unfortunately increases the associated capacitances (e.g., drain and source-to-gate capacitances and drain and source-to-bulk capacitances). If the on resistance r
on
can be sufficiently reduced by other means, however, freedom is then gained to select a larger device which will reduce the associated capacitances and thus further reduce distortion and enhance speed.
Accordingly, reduction of switch on resistance r
on
is an important consideration in the design of switched-capacitor structures. When the switches are realized as CMOS transistors, this reduction can be achieved by applying a substantial gate-to-source voltage V
gs
. Photolithographic techniques for the fabrication of modern signal conditioning systems are directed, however, to realizing greater circuit densities by the use of thinner line widths and these thinner lines also require lower supply voltages (e.g., V
DD
). This limits the available gate-to-source voltage V
gs
which in turn, makes it more difficult to realize a low on resistance r
on
.
Although it is important to reduce the magnitude of the on resistance r
on
, it is also important to keep it substantially constant during signal acquisition because, otherwise, the acquired signal is distorted and degraded. There is, accordingly, an ongoing need for circuit structures that can achieve low and constant switch on resistances r
on
in the presence of ever-reducing supply voltages.
BRIEF SUMMARY OF THE INVENTION
The present invention is directed to simple, reliable and inexpensive boost structures that operate in a charge mode and a boost mode to thereby generate a boost signal S
boost
. These goals are realized with diode, switch and buffer structures that are configured to enhance speed and obtain simplification in the generation of boost signals.
The novel features of the invention are set forth with particularity in the appended claims. The invention will be best understood from the following description when read in conjunction with the accompanying drawings.
REFERENCES:
patent: 5825230 (1998-10-01), Chen
patent: 5912560 (1999-06-01), Pasternak
patent: 5969513 (1999-10-01), Clark
patent: 6072355 (2000-06-01), Bledsoe
patent: 6118326 (2000-09-01), Singer et al.
patent: 6215348 (2001-04-01), Steensgaard-Madsen
patent: 6271715 (2001-08-01), Pinchback
patent: 6525574 (2003-02-01), Herrera
patent: 2003/0020533 (2003-01-01), Price et al.
Analog Devices Inc.
Koppel, Jacobs Patrick & Heybl
Nuton My-Trang
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