Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-11-02
2004-02-17
Pham, Long (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
Reexamination Certificate
active
06693315
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and to a method of manufacturing the same; and, more particularly, the invention relates to a technique that can effectively be applied to the manufacture of a semiconductor device, including a flattening process utilizing a CMP (Chemical Mechanical Polishing) method.
Trench isolation is one of the isolation methods employed for electrically isolating adjacent semiconductor elements. In a typical trench isolation fabrication process, grooves are provided on a semiconductor substrate which grooves become an element isolation region, and these grooves are filled with insulation films.
Trench isolation is formed, for example, using the following method. First, grooves are formed to a depth, for example, of about 0.4 &mgr;m in the element isolation region of the semiconductor substrate using a dry etching method; and, thereafter, a first insulation film is formed to a thickness, for example, of about 20 nm at the surface where the semiconductor substrate is exposed by carrying out a thermal oxidation process on the semiconductor substrate. Thereafter, a second insulation film is deposited on the semiconductor substrate to fill the inside of the grooves; and, then, the trench isolation is formed by removing the portion of the second insulation film at the outside side of the grooves and leaving the portion of the second insulation film only inside of the grooves, through polishing of the surface of this second insulation film, for example, using the CMP method.
When the width of the element isolation region becomes relatively large, the polishing rate of the second insulation film becomes high in the local area during the CMP process, and, thereby, a so-called dishing phenomenon is easily generated, whereby a “recess” is produced at the central area of the grooves. However, several methods have been proposed to improve the flatness at the surface of the second insulation film in the element isolation region by controlling the dishing phenomenon. A method of providing a dummy pattern is one of such methods.
For example, the Japanese Patent Application Laid-Open No. Hei 10(1998)-92921, corresponding to the U.S. Pat. No. 5,885,856, discloses a method in which each dummy structure is placed in a non-active device area to cause the occupation density in the non-active device area to be equal to that of the active device area, and, thereby, the polishing rate is equalized for the entire part of the semiconductor substrate surface.
Moreover, the inventors of the present invention have considered a method of placing the dummy patterns in a regular manner. The technique explained below has been considered by the inventors of the present invention and its outline is as follows.
FIG. 28
shows a first dummy pattern placing method which the inventors of the present invention have considered.
A plurality of dummy patterns DPA, are regularly placed in a dummy region (region outside of the frame indicated by the broken line in the figure) FA, where semiconductor elements are not formed, outside of the element forming region (region within the frame of broken line in the figure) DA, where the semiconductor elements are formed. A plurality of dummy patterns DPA
1
are formed to be equal in shape and size, and these dummy patterns are extensively placed with the same interval in the dummy region FA.
The element forming region DA and dummy region FA, outside of the active region AC, form element isolation region IS, and a trench isolation is usually formed in the entire part of this isolation region IS. Therefore, this method for regularly placing the dummy patterns has the inherent problem that the dishing phenomenon is easily generated during the CMP process, particularly in the dummy region FA, which is isolated from the active region AC. However, it is now possible to prevent such dishing phenomenon in the dummy region FA by placing a plurality of dummy patterns DP
1
therein, whereby the flatness at the surface of the embedding insulation film in the dummy region FA can be improved.
FIG. 29
shows a second dummy pattern placing method which the inventors of the present invention have discussed. Like the method illustrated in
FIG. 28
, a plurality of dummy patterns DPA
2
are regularly placed in the dummy region FA, where the semiconductor elements are not formed, outside of the element forming region DA, where the semiconductor elements are formed, and, thereby, the dishing in the dummy region FA can be prevented. The size of the dummy patterns DPA
2
is smaller than the size of the dummy patterns DPA
1
and the dummy patterns DPA
2
can be placed up to the dummy region FA near the boundary BL (indicated by the frame line in the figure) between the element forming region DA and dummy region FA.
SUMMARY OF THE INVENTION
However, according to an investigation by the inventors of the present invention, there has been a further problem in that, when the dummy structures are placed in the non-active device area, some dummy structures are complicated in shape and the insulation film is not perfectly embedded within the internal side of the dummy structures which are particularly defined. Moreover, it has also been formed that the time required for the manufacturing process is extended because it is necessary to additionally provide a process for removing the dummy structures that are too small to be formed.
In addition, the inventors of the present invention have also found that the following problem exists in the first dummy pattern placing method and the second dummy pattern placing method.
In the first dummy pattern placing method, since the size of the dummy patterns DPA
1
is relatively large, a region where the dummy patterns DPA
1
cannot be placed is generated in the dummy region FA near the boundary BL between the element forming region DA and dummy region FA; and, if this region is extended relatively, it is apparent that the dishing phenomenon is generated.
In the second dummy pattern placing method, since the size of the dummy patterns DPA
2
is relatively small, the dummy patterns DPA
2
may be placed up to the area near the boundary BL between the element forming region DA and dummy region FA. Thereby, since the dummy patterns DPA
2
may be placed also in the region where the dummy patterns DPA
1
cannot be placed, the second dummy pattern placing method can further improve the flatness of the surface of the embedded insulation film up to the dummy region FA near the boundary BL in comparison with the first dummy pattern placing method.
However, when the second dummy pattern placing method is introduced, the number of dummy patterns DPA
2
placed in the dummy region FA increases, and, thereby, the coordinate data required for generating a mask remarkably increases. As a result, there arises a problem in that the arithmetic processing time in computer used for generating a mask pattern increases, and, moreover, the time required for drawing the patterns on the mask substrate also increases, with the result that the throughput in the formation of a mask is remarkably deteriorated. Particularly, when the second dummy pattern placing method is employed for ASIC (Application Specific Integrated Circuit: integrated circuit for particular application), the time required to generate the mask is extended, with the result that a problem remains for development of ASIC within a short period of time.
It is therefore an object of the present invention to provide a technique to improve the flatness of the surface of members embedded in a plurality of recesses.
It is another object of the present invention to provide a technique to improve the flatness of the surface of members embedded in a plurality of recesses without extension of the time required for manufacturing the semiconductor device.
The objects explained above, other objects and novel features of the present invention will become more apparent from the following description of the present invention and the accompanying drawings.
The typical aspects of the
Kuroda Kenichi
Watanabe Kozo
Yamamoto Hirohiko
Farahani Dana
Pham Long
Renesas Technology Corporation
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