Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Die bond
Reexamination Certificate
2001-04-05
2002-10-15
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Die bond
C257S758000
Reexamination Certificate
active
06465895
ABSTRACT:
BACKGROUND OF THE INVENTION
Bonding pads are interconnect structures formed on an integrated circuit to provide an interface between internal circuitry and external pin leads of the integrated circuit package. Bonding wires provide for electrical contact between the pins and bonding pads. During application of a bonding wire, as the bonding wire is lowered into position on the bonding pad, mechanical stress is exerted on the bonding pad by the micropositioner machine used to position the wire. The stress, in turn, causes cracks and voids to form in the underlying insulator layer below the bonding pad. This, in turn, can expose an underlying metal layer, leading to possible deleterious effects such as corrosion and shorting of the underlying layer.
A cross-sectional view of a conventional bonding pad configuration is provided in FIG.
1
. In this example, a lower metal layer
22
is provided on a semiconductor substrate. An interlayer insulating film (referred to herein as an inter-layer dielectric (ILD))
24
is formed over the metal later
22
. A bonding pad
30
is formed on the ILD, and a passivation layer
28
is formed about the bonding pad
30
.
A wire
34
is bonded to the bonding pad
30
at solder joint
32
using a pressurized thermal bonding process. During the bonding procedure, downward force is exerted on the bonding pad, which generates cracks and voids
36
in the underlying ILD. The stress tends to be concentrated at the horizontal edges of the bonding pad; rather than at the central portions. For this reason, cracks emanating outwardly from the edge regions can expand into adjacent regions of the semiconductor circuit. As the cracks emanate, they can actually become larger in width as the distance from the respective source increases. Such cracks can form an opening to expose the underlying metal layer, leading to possible corrosion, and can further extend through underlying metal layers, which can isolate regions of the metal layers, leading to circuit failure.
SUMMARY OF THE INVENTION
The present invention is directed to a semiconductor structure, and a fabrication technique for forming such a structure, configured to confine and prevent expansion of cracking of the insulating layer below a bonding pad, that are generated as a result of the bonding process. In a first embodiment, the present invention includes a vertical frame, formed, for example of conductive material, surrounding the outer perimeter of the bonding pad, and extending through an underlying insulating layer. A horizontal frame lies below the vertical frame. Together, the vertical frame and horizontal frame confine cracks emanating below the bonding pad within the frame region. In a second embodiment, horizontal and vertical portions of the frame are formed by a conductive layer provided in an opening formed in the insulating layer. Since the isolation frame prevents cracks from expanding into surrounding regions of the integrated circuit, overall process yield and reliability are improved.
In a first aspect, the present invention comprises a semiconductor bonding pad structure and a method for forming such a structure. An insulating layer is first provided and a bonding pad is formed on the insulating layer, the bonding pad having a horizontal boundary. At least one vertical frame formed of a conducting material is provided vertically through the insulating layer, the at least one vertical frame being horizontally positioned beyond the horizontal boundary of the bonding pad.
In a preferred embodiment, the present invention further comprises a horizontal frame extending horizontally through the insulating layer below the bonding pad. The horizontal frame preferably comprises a conducting material, for example selected from the group of a materials consisting of metal, polysilicon, and silicide. The at least one vertical frame may be positioned on, and in contact with, the horizontal frame.
The bonding pad may be shaped in a geometry including stress concentration regions, in which case, the at least one vertical frame is positioned proximal to the stress concentration regions. The at least one vertical frame may comprise multiple vertical frame segments positioned locally with respect to the stress concentration regions. The at least one vertical frame preferably substantially surrounds the horizontal boundary of the bonding pad, and extends through the entire depth of, or partially through, the insulating layer.
The at least one vertical frame may comprise a plurality of vertical frame segments vertically stacked through multiple insulating layers of the semiconductor device. A buffer layer may be formed on the insulating layer, the buffer layer having a horizontal boundary, and an intermediate insulating layer may be provided on the buffer layer, whereby the bonding pad is provided on the intermediate insulating layer above the buffer layer. In this case the at least one vertical frame may extend vertically through the insulating layer, positioned beyond the horizontal boundary of the buffer layer. The at least one vertical frame extension may extend vertically through the intermediate insulating layer above the at least one vertical frame and being horizontally positioned beyond the horizontal boundary of the bonding pad. Contact plugs may formed through the intermediate insulating layer, electrically contacting the buffer layer and bonding pad.
In a second aspect, the present invention is directed to a semiconductor bonding pad structure, and a method for forming the structure. The structure includes a horizontal frame having a horizontal boundary; an insulating layer above the horizontal frame; a bonding pad on the insulating layer above the horizontal frame, the bonding pad having a horizontal boundary; and at least one vertical frame provided vertically through the insulating layer, the at least one vertical frame being horizontally positioned beyond the horizontal boundary of the bonding pad.
In a third aspect, the present invention is directed to a semiconductor bonding pad structure and method for forming the structure. A first insulating layer is provided on an underlying layer, the insulating layer having an opening therein, the opening having a substantially horizontal lower surface and a substantially vertical side surface. A conductive layer is provided in the opening, the conductive layer having a horizontal portion formed on the horizontal lower surface of the opening and a vertical portion formed on the vertical side surface of the opening. A second insulating layer is provided on the conductive layer. A bonding pad is provided on the second insulating layer vertically positioned above the horizontal portion of the conductive layer and horizontally positioned between the vertical portion of the conductive layer.
The underlying layer may comprises a substrate or an underlying insulating layer. The underlying layer may comprise an intermediate conductive layer having, for example, an etch selectivity with respect to the first insulating layer.
The upper surface of the vertical portion of the conductive layer defines an upper rim wherein the bonding pad is preferably vertically positioned below, at, or above the upper rim. The second insulating layer preferably forms a depression extending into the opening and the bonding pad may be positioned within the depression. The depression may include inner side walls, wherein the bonding pad has an area less than the area defined between the inner side walls of the opening.
A buffer layer may be formed on the second insulating layer, the buffer layer having a horizontal boundary. An intermediate insulating layer may be provided on the buffer layer. In this case, the bonding pad is provided on the intermediate insulating layer above the buffer layer. Contact plugs may be formed through the intermediate insulating layer, electrically contacting the buffer layer and bonding pad.
REFERENCES:
patent: 5036383 (1991-07-01), Mori
patent: 5288661 (1994-02-01), Satoh et al.
patent: 5502337 (1996-03-01), Nozaki
patent: 5736791 (1998-04-01), F
Hong Weon-cheol
Min Eun-young
Park Young-hoon
Mills & Onello LLP
Tran Long K.
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