Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-01-18
2001-10-23
Picardat, Kevin M. (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S597000, C438S611000, C438S613000
Reexamination Certificate
active
06306750
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to a method used to form a bonding pad, used to allow electrical communication between an overlying gold wire, and underlying circuitry of an integrated circuit, and more specifically to a method used to create a metal mesh pattern, underlying the bonding pad, used to increase the surface area, and the roughness of the overlying bonding pad.
(2) Description of the Prior Art
Wire bonds, physically, as well as electrically, connected to underlying circuitry, of semiconductor chips, are used to connect the specific semiconductor chip to packaging elements, such as printed circuit board, or ceramic modules. A bond pad structure, is usually formed overlying the top conductive layer, of the semiconductor chip, and used to accept an overlying metal, or gold wire bond structure. In most cases a group of metal studs are used between, and to connect the bond pad structure, to the top conductive layer, of a semiconductor chip, with the metal studs formed in via holes, that in turn have been formed in an inter-metal dielectric, (IMD), layer. However the large, exposed, surface area of IMD layer, located surrounding the smaller regions of metal studs, can result in defect formation, or cracking of the IMD layer, as a result of the large bonding force, experienced during the metal wire bonding procedure, where the large bonding forces is distributed throughout the overlying bond pad structure.
This invention will describe a process for fabricating a metal mesh pattern, to be used in place of a group of individual studs. The presence of the metal mesh pattern, creates isolated islands of IMD, reducing the area of the exposed IMD, thus reducing the bonding force on the IMD) shape. In addition the metal mesh pattern is formed with indented, or notched, top surface features, which increases the surface area of the metal mesh structures, when compared to metal mesh patterns, comprised with smooth top surface topographies. This in turn result in a roughened top surface of the overlying, bond pad structure, allowing improved bondability characteristics, for the subsequent metal, or gold wire bonds, to be realized. Prior art, such Shiue et at, in U.S. Pat. No. 5,700,735, describe the formation of, and the use of, diamond shaped via plug structures, to improve the characteristics of an overlying bond pad structure. However that prior art does not describe the metal mesh pattern, with indented, or notched top surfaces, used to allow an overlying, bond pad structure, with increased top surface roughness, to be achieved.
SUMMARY OF THE INVENTION
It is an object of this invention to form a metal wire bond, to an underlying bond pad structure, which in turn communicates with underlying circuitry, of a semiconductor chip.
It is another object of this invention to use a metal mesh pattern, formed in an IMD layer, located between the overlying bond pad structure, and the underlying circuitry of the semiconductor chip, and used to reduce the exposed surface area of the IMD layer, when compared to counterparts fabricated using a group of metal via plugs, thus reducing the bonding force distributed on the IMD layer, during the metal wire bond procedure.
It is yet another object of this invention to form the metal mesh pattern with an indented, or notched, top surface topography, to increase the surface roughness of the overlying bond pad structure, thus improving adhesion of the metal wire bond, to the underlying bond pad structure.
In accordance with the present invention a method of forming a metal mash pattern, in an IMD layer, located between an overlying, bond pad structure, and the underlying circuitry of a semiconductor chip, wherein the top surface of the metal mesh pattern is indented, or notched, is described. An IMD layer is formed on an upper level metal interconnect pattern, of a semiconductor chip, followed by the opening of a mesh, or grid pattern, in the IMD layer, exposing regions of the top surface of the upper level metal interconnect pattern. A metal layer, such as tungsten is deposited, not completely filling the mesh or grid pattern, in the IMD layer, resulting in an indented, or notched, top surface, for regions of the metal layer, located in the mesh openings. Removal of regions of the metal layer, from the top surface of the IMD layer, via a chemical mechanical polishing, (CMP), procedure, or via a reactive ion etch back procedure, results in a metal, or tungsten, mesh pattern, in the IMD layer, overlying and contacting the regions of the upper level metal interconnect pattern, exposed in the mesh pattern opening, with the metal mesh pattern featuring an indented, or notched, top surface topography. Deposition and patterning, of a metal layer, such as an aluminum—copper layer, is next addressed, resulting in a bond pad structure, with a roughened top surface topography, overlying, and contacting, the metal mesh pattern. A metal, or gold wire bond, is then made to the roughened top surface, of the bond pad structure.
REFERENCES:
patent: 5985765 (1999-11-01), Hsiao et al.
patent: 6043144 (2000-03-01), Kuo
Huang Yung-Sheng
Hwang Ruey-Lian
Lin Chiu-Ching
Lu Chun-Hung
Ackerman Stephen B.
Collins D. M.
Picardat Kevin M.
Saile George O.
Taiwan Semiconductor Manufacturing Company
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