Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2006-11-14
2006-11-14
Geyer, Scott B. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
Reexamination Certificate
active
07135395
ABSTRACT:
A method is disclosed of forming a bonding pad that is immune to IMD cracking. A partially processes semiconductor wafer is provided having all metal levels completed. A blanket dielectric layer is formed over the uppermost metal level. Patterning and etching said dielectric layer horizontal and vertical arrays of trenches are formed passing through the dielectric layer and separating the dielectric layer into cells. The trenches are filled with a conducting material and, after performing CMP, bonding metal patterns are deposited. Wires are bonded onto said bonding metal patters, after which a passivation layer is formed.
REFERENCES:
patent: 5731243 (1998-03-01), Peng et al.
patent: 6002179 (1999-12-01), Chan et al.
patent: 6025277 (2000-02-01), Chen et al.
patent: 6232662 (2001-05-01), Saran
patent: 6236114 (2001-05-01), Huang et al.
patent: 6313540 (2001-11-01), Kida et al.
patent: 6465895 (2002-10-01), Park et al.
Liu Chung
Liu Yuan-Lung
Shiue Ruey-Yun
Geyer Scott B.
Taiwan Semiconductor Manufacturing Co.
LandOfFree
Bonding pad structure to minimize IMD cracking does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Bonding pad structure to minimize IMD cracking, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Bonding pad structure to minimize IMD cracking will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3628321