Bonding pad structure of semiconductor device

Details Bonding pad structure of semiconductor device Bonding pad structure of semiconductor device

1999-09-29

2001-10-02

Clark, Jhihan B (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Ball or nail head type contact, lead, or bond

C257S758000, C257S750000

Reexamination Certificate

active

06297563

ABSTRACT:

This application is based on Japanese patent application No. HEI 10-294459 filed on Oct. 1, 1998, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
a) Field of the Invention
The present invention relates to a bonding pad structure of a semiconductor device such as an LSI, and more particularly to a bonding pad structure having n (n is an integer of 3 or larger) pad layers and (n−1) interlayer insulating films.
b) Description of the Related Art
A most common bonding pad structure has large bonding pads formed on the highest-level insulating film among a plurality of insulating films. With such a bonding pad lamination structure, if a lamination film including a coated insulating film such as organic or inorganic SOG (spin on glass) is used as the insulating film or films under the pad layer, peel-off or cracks of the coated insulating film may occur because of heat and pressure during the bonding, thereby lowering the reliability.
In order to solve this problem, semiconductor devices having a bonding pad area such as shown in
FIGS. 8
to
11
are known (refer to JP-A-9-219451).
In the semiconductor device shown in
FIG. 8
, a first-level (first-layer) insulating film
2
is formed on the surface of a semiconductor substrate
1
. On this first-level insulating film
2
, a plurality of first-level wiring layers
3
a
and a plurality of first-level pad layers
3
b
are formed. The wiring layer
3
a
is formed in an inner wiring area A including an integrated circuit formed on the semiconductor substrate
1
. The pad layer
3
b
is formed in a bonding pad area B disposed around the inner wiring area A.
On the first-level insulating film
2
, a first-level interlayer insulating film
4
is formed covering the plurality of wiring layers
3
a
and pad layers
3
b
. The upper surface of the first-level interlayer insulating film
4
is planarized by chemical mechanical polishing (CMP). A contact hole
4
A and a plurality of contact holes
4
B are formed through the first-level interlayer insulating film
4
by photolithography and dry etching in the areas corresponding to the wiring layer
3
a
and pad layer
3
b
. First-level contact plugs
5
a
and
5
b
are filled in the contact holes
4
A and
4
B. These contact plugs
5
a
and
5
b
are formed by forming a conductive layer of tungsten (W) or the like on the insulating film
4
and in the contact holes
4
A and
4
B, and thereafter etching back the conductive layer until the upper surface of the insulating film
4
is exposed.
On the first-level interlayer insulating film
4
, a second-level wiring layer
6
a
and a second-level pad layer
6
b
are formed. The wiring layer
6
a
is connected via the contact plug
5
a
to the wiring layer
3
a
, and the pad layer
6
b
is connected via a plurality of contact plugs
5
b
to the pad layer
3
b.
On the first-level interlayer insulating film
4
, a second-level interlayer insulating film
7
is formed covering the second-level wiring layer
6
a
and second-level pad layer
6
b
. The upper surface of the second-level interlayer insulating film
7
is planarized by CMP. A contact hole
7
A and a plurality of contact holes
7
B are formed through the second-level interlayer insulating film
7
by photolithography and dry etching in the areas corresponding to the second-level wiring layer
6
a
and second-level pad layer
6
b
. Second-level contact plugs
8
a
and
8
b
are filled in the contact holes
7
A and
7
B. These contact plugs
8
a
and
8
b
are formed by a process similar to that of forming the first-level contact plugs
5
a
and
5
b
described above.
On the second-level interlayer insulating film
7
, a third-level wiring layer
9
a
and a third-level pad layer
9
b
are formed. The third-level wiring layer
9
a
is connected via the second-level contact plug
8
a
to the second-level wiring layer
6
a
, and the third-level pad layer
9
b
is connected via a plurality of second-level contact plugs
8
b
to the second-level pad layer
6
b.
In the semiconductor device shown in
FIG. 9
, the wring structure in the inner wiring area A is similar to that in the inner wiring area A shown in FIG.
8
. In
FIG. 9
, like elements to those shown in
FIG. 8
are represented by using identical reference symbols, and the description thereof is omitted.
In the bonding pad area B shown in
FIG. 9
, the insulating film
4
is formed on the insulating film
2
, and the insulating film
7
is formed on the insulating film
4
. On the insulating film
7
, a pad layer
9
b
is formed by using the same process as that of forming the wiring layer
9
a.
In the semiconductor device shown in
FIG. 10
, the wring structure in the inner wiring area A is similar to that in the inner wiring area A shown in FIG.
8
. In
FIG. 10
, like elements to those shown in
FIG. 8
are represented by using identical reference symbols, and the description thereof is omitted.
In the bonding pad area B shown in
FIG. 10
, the insulating film
4
is formed on the insulating film
2
, and on the insulating film
4
the pad layer
6
b
is formed by using the same process as that of forming the wiring layer
6
a.
On the insulating film
4
, the insulating film
7
is formed covering the wiring layer
6
a
and pad layer
6
b
. The upper surface of the insulating film
7
is planarized by CMP. Contact holes
7
A and
7
B are formed through the insulating film
7
by photolithography and dry etching in the areas corresponding to the wiring layer
6
a
and layer
6
b
. The contact hole
7
S is made larger in size than the contact hole
7
A for the later process of bonding a bonding wire.
After a conductive layer of W or the like is formed on the insulating film
7
and in the contact holes
7
A and
7
S, the conductive layer is etched back until the upper surface of the insulating film is exposed. A contact plug
8
a
made of conductive material such as W is therefore formed in the contact hole
7
A. At this time, although a thin conductive layer (not shown) is left on the side wall of the contact hole
7
S, most of the conductive layer are etched and removed during the etch-back process so that the upper surface of the pad layer
6
b
is exposed in the contact hole
7
S.
A wiring layer is deposited on the insulating film
7
, covering the contact plug
8
a
and the contact hole
7
S, and patterned to form a wiring layer
9
a
and a pad layer
9
b
. The pad layer
9
b
directly contacts the pad layer
6
b
in the contact hole
7
S.
In the semiconductor device shown in
FIG. 11
, on the insulating film
2
covering the surface of the substrate
1
, the first-level wiring layer
3
a
and the first-level pad layer
3
b
are formed by the method similar to that described with reference to FIG.
8
. On the insulating film
2
, the insulating film
4
is formed covering the wiring layer
3
a
and pad layer
3
b
. The upper surface of the insulating film
4
is planarized by CMP.
Similar to the contact holes
7
A and
7
S described with reference to
FIG. 10
, a small size contact hole
4
A and a large size contact hole
4
S are formed through the insulating film
4
in the areas corresponding to the wiring layer
3
a
and pad layer
3
b
. Similar to the contact plug
8
a
described with reference to
FIG. 10
, a contact plug
5
a
made of conductive material such as W is formed in the contact hole
4
A. Similar to the wiring layer
9
a
and pad layer
9
b
described with reference to
FIG. 10
, a second-level wiring layer
6
a
and a second-level pad layer
6
b
are formed on the insulating film
4
. The wiring layer
6
a
is connected via the contact plug
5
a
to the wiring layer
3
a
, and the pad layer
6
b
is directly connected to the pad layer
3
b
in the contact hole
4
S.
On the insulating film
4
, an insulating film
7
is formed covering the wiring layer
6
a
and pad layer
6
b
. The upper surface of the insulating film
7
is planarized by CMP. A small size contact hole
7
A corresponding to the wiring layer
6
a
and a large size contact hole
7
S corresponding t

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