Bonding pad structure and manufacturing method thereof

Details Bonding pad structure and manufacturing method thereof Bonding pad structure and manufacturing method thereof

2011-02-15

2011-02-15

Potter, Roy K (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257SE23023, C257S773000, C438S612000

Reexamination Certificate

active

07888802

ABSTRACT:
A bonding pad structure of a semiconductor device and a method of manufacturing the same reduce the likelihood of peel-off defects from occurring. The bonding pad structure includes a substrate, an interlayer insulation layer on the substrate, an upper wiring layer on the interlayer insulation layer, and a plurality of lower wiring layers disposed in the interlayer insulation layer between the upper wiring layer and the substrate and configured to prevent the interlayer insulation layer from cracking especially during a wire bonding process in which a wire is bonded to the upper wiring layer. For example, the respective areas occupied by the lower wiring layers sequentially increase in the interlayer insulation layer in a downward direction from the upper wiring layer towards the substrate. Also, each of the lower wiring layers may project further inwardly toward a central part of the bonding pad than the lower layer of wiring disposed above it in the interlayer insulation layer.

REFERENCES:
patent: 5149674 (1992-09-01), Freeman et al.
patent: 5739587 (1998-04-01), Sato
patent: 6207547 (2001-03-01), Chittipeddi et al.
patent: 7211902 (2007-05-01), Yamaha
patent: 7232705 (2007-06-01), Righter
patent: 2002-222811 (2002-08-01), None
patent: 1020000009043 (2000-02-01), None
patent: 100741910 (2007-07-01), None

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