Bonding pad arrangement method for semiconductor devices

Details Bonding pad arrangement method for semiconductor devices Bonding pad arrangement method for semiconductor devices

2005-09-27

2005-09-27

Williams, Alexander Oscar (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Wire contact, lead, or bond

C257S786000, C257S773000, C257S730000, C257S775000, C257S776000, C257S777000, C257S696000, C257S691000, C257S698000, C257S674000, C029S827000

Reexamination Certificate

active

06949837

ABSTRACT:
A variety of pad arrangements are provided for semiconductor devices for reducing the likelihood of bonding failures, particularly those due to shorts, and/or for reducing the difference in length between bonding wires to decrease signal skew during operation of the semiconductor device and improve signal integrity.

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patent: 6008532 (1999-12-01), Carichner
patent: 6303948 (2001-10-01), Kudou et al.
patent: 03-109747 (1991-05-01), None
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patent: 6-37131 (1994-02-01), None
patent: 8-330351 (1996-12-01), None
patent: 10-74786 (1998-03-01), None

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