Active solid-state devices (e.g. – transistors – solid-state diode – Alignment marks
Reexamination Certificate
2001-07-23
2002-10-15
Whitehead, Jr., Carl (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Alignment marks
C257S734000, C257S798000
Reexamination Certificate
active
06465898
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to integrated circuits, more particularly to alignment features which facilitate wire bonding to integrated circuits, and even more particularly to circuits having the bonding surface positioned atop active circuitry.
BACKGROUND OF THE INVENTION
Integrated circuit (IC) devices include a plurality of metallized bond pads where electrical connections to the device are made, either by wire bonds, flip chip bump connections, or flexible contacts to metal bumps, such as TAB (Tape Automated Bonding). Typically, the bond pads as well as their buses are placed in the periphery of the integrated circuit, outside the area containing active components. This conventional structure for the bond pads adds to the required area of the IC, which in turn reduces production efficiency, increases the size of each IC, and adds to the resistance current path.
Recently integrated circuits having wire bonding surfaces or pads positioned directly over active circuitry have been disclosed in U.S. Pat. No. 6,144,100 granted Nov. 7, 2000, U.S. patent application No. 60/221,051 filed on Jul. 27, 2000, and U.S. patent application Ser. No. 09/611,623 filed on Jul. 7, 2000. The structure of these devices assumes at least one metallization layer for active circuitry covered by an insulating, protective coating through which vias are formed to provide a means for interconnection between the active metallization layer on the IC, and a thicker, multilayer of metals which form a bonding surface. The multilayer of metals includes a seed metal layer, such as titanium, a plated support layer, such as copper, and a bonding layer, such as gold or palladium. The support layer is a relatively thick layer, in the range of 10-30 microns which serves to absorb stresses of the wire bonding process, and to protect the underlying active circuitry. The multilayer of metals provides advantages to the device in thermal enhancement, in minimizing the number of external output contacts by providing common power or ground connections, and in minimizing chip size by eliminating some or all of the perimeter bond pads. Alternately, bonding over active circuits has been reported wherein a dielectric material provides the support layer to minimize stresses, and one or more layers of metal provide the bonding surface. (Heinen, G., Stierman, R. J., Edwards, D. and Nye, L.
IEEE Proc. of
44
th ECTC,
1994). Flip chip devices are frequently designed with solder bump contacts positioned directly over active circuits. In each of these device types, the ability to visually detect reference or alignment marks on the active surface of the chip may be obscured by thick passivation, and metallization.
In the process of wire bonding a semiconductor device having either conventional bond pads on the perimeter of the chip, or on a bonding surface over the active circuitry, it is necessary to input precise bonding coordinates to a pattern recognition system of an automated wire bonding equipment. The most usual method of inputting these coordinates is to perform a teaching operation in which the first object to be bonded is magnified by a camera, and displayed on a monitor. An operator carries out an operation by specifying the coordinates to be bonded while viewing the image on the monitor. The X-Y stage of the bonder is adjusted so that the starting point of the first wire is displayed on the monitor, and the coordinates stored. Next the same teaching operation is carried out for the coordinates of the end point of the wire. Typically, the start point is the bonding pad on the chip, and the end point is a lead finger on a lead frame. The procedure is carried out sequentially for all the wires to be bonded. Reference or alignment marks are used as an aid or guide for carrying out the alignment. Typically the reference marks on the IC are a cross, a rectangle, or the bond pads themselves patterned in the active metal layer, but such marks are not standardized throughout the industry.
Accuracy of the bond wire position is related to the ability of the operator to view the alignment marks, and make accurate input to the pattern recognition system. Lighter colored patterns, or reflective features generally provide better alignment marks owing to the higher level of contrast with a darker non-bonding surfaces, particularly as viewed by vertical lighting which is commonly used with wire bond equipment. Bonding surfaces positioned over active circuits diffuse visibility to underlying bond reference marks on the active area, and exhibit very little contrast across the device surface, thereby causing accurate bonding alignment to be significant problem. The bond wires must be positioned in precise locations, according to the device design, and must avoid the vias connecting the bonding surface to the active circuit.
Flip chip bonding of solder bumps to receiving pads on a substrate requires only a single bond process for all input/output (I/O) contacts, but alignment does suffer from issues of depth of focus because of the raised bumps, and inability to clearly recognize specific corner locations, particularly on those devices having symmetrical contacts because of thick passivation and metallization on the chip surface. Similar issues are found for other bumped devices, such as TAB bonded circuits.
Lack of ability to readily recognize the reference or alignment marks slows the bonder teaching process, as well as results in bonding failures at a very costly point in the fabrication of an IC device. Further, as use of subcontract IC package manufacturing for many different IC fabricators has become more prevalent, standardization of the alignment targets is a more important concern for yield, throughput, and overall assembly cost.
Because of the aforementioned issues, and the anticipation of an increase in the number of integrated circuit chips with bonding surfaces covering the active circuit, an alignment or reference mark on the surface of integrated circuits which is readily visible using vertical lighting of an automated bonding equipment would be advantageous to the industry, and in particular for those circuits having a metallized bonding surface atop the active circuitry.
SUMMARY OF THE INVENTION
It is an object of the invention to provide alignment marks on the surface of an integrated circuit which are readily visible by wire bonding equipment.
It is an object of the invention to provide alignment marks for bonding to ICs having a metallized bonding surface atop active circuitry.
It is an objective of the invention to provide exposed alignment marks having good contrast from that of the major surface of the chip.
It is an object of the invention that the alignment marks are small, and require the minimum amount of chip area.
It is further an objective of the invention to provide a pair of unique reference marks in opposite corners of the chip.
It is further an objective of the invention to provide standardized reference marks which are unique as bonding alignment features, and are the same across a spectrum of circuit types, and bonding surfaces.
It is further an objective of the invention to provide standardized bond reference marks which are applicable to flip chip, other bumped chips, or chips having conventional wire bond pads.
These objectives will be met by fabricating alignment marks positioned on diagonal corners of the chip, each mark consisting of a touching dual square patterns which are rotated about 90 degrees from each other in the opposite chip corners. The unique positioning of the marks, as well as the rotation provides both gross chip position features useful in mounting the chip on a lead frame, as well as fine alignment set-up or teaching aids for wire bonding.
The features of the alignment mark are fabricated in the top active metallization of the IC chip, and are not covered by passivation coating or additional metal layers, such as those metal layers used for bonding over active circuits. The exposed alignment marks provide high contrast to either the active metal
Grant David
Hastings Roy A.
Hnilo Laura A.
Pierce Mike P.
Brady III W. James
Jr. Carl Whitehead
Rose Kiesha
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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